JPS641066B2 - - Google Patents

Info

Publication number
JPS641066B2
JPS641066B2 JP15993580A JP15993580A JPS641066B2 JP S641066 B2 JPS641066 B2 JP S641066B2 JP 15993580 A JP15993580 A JP 15993580A JP 15993580 A JP15993580 A JP 15993580A JP S641066 B2 JPS641066 B2 JP S641066B2
Authority
JP
Japan
Prior art keywords
semiconductor substrate
oxide film
impurity layer
high concentration
concentration impurity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP15993580A
Other languages
Japanese (ja)
Other versions
JPS5784171A (en
Inventor
Fumio Tobioka
Shoichi Kitane
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP15993580A priority Critical patent/JPS5784171A/en
Publication of JPS5784171A publication Critical patent/JPS5784171A/en
Publication of JPS641066B2 publication Critical patent/JPS641066B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals

Description

【発明の詳細な説明】 本発明は電力用の半導体基板の製造方法の改良
に関する。 裏面よりコレクタ電極を取出す半導体素子では
コレクタの飽和抵抗を減少させる為に裏面にはコ
レクタと同じ導電型の高濃度の不純物層を必要と
する。このような半導体装置の半導体基板を製造
する方法としては、コレクタと同じ導電型の不純
物(NPN型半導体素子でN+層)を半導体基体の
両面に拡散し、その後ラツピングにより片面拡散
層を削取りにさらにミラーラツピングにより破砕
層を取り除いてその表面をミラー仕上げする方法
が知られている。このようにして製造された半導
体基板は、一般にワンサイドラツピング仕上げウ
エハ(OSLウエハ)と称せられている。 以下、従来の半導体基板製造方法を第1図A乃
至同図Eを参照して説明する。まず、第1図Aに
示す如く、例えばN型の厚さ500μm、#1000ラ
ツプ仕上げの半導体基体1を用意する。次に、同
図Bに示す如く、この半導体基体1の両面に、
N+型の不純物を例えばオキシ塩化リン(POCl3
を拡散源として1200℃の温度下で3時間N+不純
物の堆積によつて高濃度不純物層2(シート抵抗
2.3〜0.5Ω/、N+深さ15μm)として形成する。
次に同図Cに示す如く、これを1270℃の温度で
270時間拡散炉に投入し高濃度不純物層2のスラ
ンピングを行ない拡散深さが190μmの高濃度不
純物層3を得る。次に、同図Dに示す如く、
#1000ラツプにて表面から220μmまでを削取り
片面の高濃度不純物層3を除く。さらに高濃度不
純物層3の表面の破砕層を取り除き表面をミラー
仕上げにする為ミラーラツピングを行ない、同図
Eに示す如く、コレクタ領域となるN-層4の層
厚が60μmで厚さが250μmの表面にミラー仕上げ
が施された半導体基板5を得る。 しかしながら、従来の半導体基板の製造方法で
は、次のような欠点がある。 250μm仕上げ厚さの半導体基板を製作す
るには500μmの内厚を有する厚い半導体基体
1が必要であり半導体基体1のロスが多い。 片面の削取り量が200μm以上必要であり、
#1000ラツプで削取り後にミラーラツプ仕上げ
と機械的仕上げを必要とするため、電力用半導
体素子を作つた場合基板のライフタイムの低下
を招く。 本発明は、かかる点に鑑みてなされたもので薄
肉の半導体を用いてライフタイムの長い半導体基
板を容易に製造することができる半導体基板の製
造方法を見出したものである。 以上、本発明の一実施例を図面を参照しながら
説明する。まず、第2図Aに示す如く、厚さ
270μm#1000ラツプ仕上げのN導電型の半導体
基体10を用意する。次に、同図Bに示す如くこ
の半導体基体10の両面にN+型の不純物を例え
ば、オキシ塩化リンPOCl3を拡散源として1200℃
の温度で3時間酸化性雰囲気中にて堆積し、高濃
度不純物層11(シート抵抗0.3〜0.5Ω/□拡散
深さ15μm)を形成する。次に、同図Cに示す如
く、1000℃の温度で2分間スチームを流しながら
酸化を行い、高濃度不純物層11の表面に第1酸
化膜厚12を形成する。この第1酸化膜12は、
次のN+スランピング拡散にて高濃度不純物層1
1からのリンの飛出しを防止するためのものであ
り、その膜厚は8000Å〜10000Åに設定するのが
望ましい。次にこれの裏面をワツクス等で保護し
た後、弗酸液にて片側の表面の第1酸化膜12を
取り除く。さらに除去したその表面にケミカルエ
ツチングを施す。この場合エツチング仕上げ面
は、半導体素子製造工程でホトンジストによる酸
化膜エツチング工程等があるためミラー仕上げ面
とすることが必要である。また、半導体基体10
内が均一でしかも片側の高濃度不純物層11が確
実に取り除けるように行なう。例えば容量比が弗
酸:硝酸:酢酸=1:2:1の混酸エツチング液
を使用し液温15℃にて200秒間エツチングし、エ
ツチング量30μmとする。 その後同図Dに示す如く、裏面の保護用ワツク
スをトリクレン処理にて除く。次に、同図Eに示
す如く、ミラーエツチングされた表面に第2酸化
膜13を形成する。第2酸化膜13は、例えば
1000℃のスチーム雰囲気中にて4時間に亘つて酸
化により形成しその膜厚は、10000〜11000Åとす
る。次に、第3図に示す如く、第1酸化膜12、
高濃度不純物層11及び第2酸化膜13を形成し
た半導体基体10を多数枚用意して、これを第1
酸化膜12同士及び第2酸化膜13同士が重なる
ように背合わせに突合わせてすき間ができないよ
うにガイド板14で加圧しながら一体に固定して
スタツク15を組立てる。ガイド板14間には50
〜100枚の半導体基体10を背合わせの状態で設
ける。次いで、このスタツク15を1270℃の酸化
性雰囲気中に270時間設置し、高濃度不純物層1
1の拡散深さが190μmに達するまでスタツク拡
散を施す。スタツク拡散後、背合せの状態で一体
に密着された半導体基体10を弗酸液に浸漬し、
第1酸化膜12及び第2酸化膜13を溶解して除
去し、第2図Fに示す如く、表面がミラーエツチ
ング仕上げされた半導体基板16を得る。 このようにこの半導体基板の製造方法によれ
ば、薄肉の半導体基体10を用いて、表面がケミ
カルミラーエツチングで仕上げられた半導体基板
16を容易に得ることができる。また、高濃度不
純物層11の表面に第1酸化膜12を片面エツチ
ング前に付けたことを、片面エツチング後にエツ
チングされた露出表面第2酸化膜13を付けたこ
と、及び多数枚の半導体基体10を第1酸化膜1
2と第2酸化膜13で背合せにスタツクしてガイ
ド板14で圧力を加えながら一体に密着せしめて
高濃度不純物層11のスタツク拡散を行うように
したことにより、第4図に示す如く高濃度不純物
層11中の不純物が外部拡散して半導体基体10
中に高濃度不純物領域16aを形成するのを防止
することができる。さらに、高濃度不純物層11
のスタツク拡散後に200μm以上片面を削り取る
必要がないため、ラツプイングを行なわずに30μ
m程度の片面ケミカルエツチングによつてミラー
面を形成することができる。また、ケミカルエツ
チングによつてミラー面を形成できるので、従来
法の機械的表面仕上げに比べて破砕層及び歪み層
を減少させることができる。その結果、第5図に
示す如く、プレナー構造でP−N接合を形成する
不純物領域17を表面から30〜40μmと深い所に
形成して電極を設けた半導体装置18を製造する
ことができる。この半導体基体16のライフタイ
ムの分布は第6図Bに示す通りであり、同図Aに
示す従来法により製造された半導体基板のライフ
タイムの分布図に比べて遥かに長いライフタイム
を有する。 尚、実施例ではNPN型の半導体基板に付いて
説明したが、勿論PNP型半導体基板に付いても
同様に適用できる。 以上説明した如く、本発明に係る半導体基板の
製造方法によれば、薄肉の半導体基体を用いてラ
イフタイムの長い半導体基板を容易に製造するこ
とができるものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a method of manufacturing a semiconductor substrate for power use. In a semiconductor device in which a collector electrode is taken out from the back surface, a highly concentrated impurity layer of the same conductivity type as the collector is required on the back surface in order to reduce the saturation resistance of the collector. A method for manufacturing a semiconductor substrate for such a semiconductor device is to diffuse impurities of the same conductivity type as the collector (N + layer in an NPN semiconductor element) onto both sides of the semiconductor substrate, and then scrape off the diffusion layer on one side by wrapping. Furthermore, a method is known in which the crushed layer is removed by mirror wrapping and the surface is mirror-finished. Semiconductor substrates manufactured in this manner are generally referred to as one-side wrapping finished wafers (OSL wafers). Hereinafter, a conventional method for manufacturing a semiconductor substrate will be explained with reference to FIGS. 1A to 1E. First, as shown in FIG. 1A, for example, an N-type semiconductor substrate 1 having a thickness of 500 μm and a #1000 lap finish is prepared. Next, as shown in FIG. B, on both sides of this semiconductor substrate 1,
N + type impurities such as phosphorus oxychloride ( POCl3 )
The high concentration impurity layer 2 (sheet resistance
2.3 to 0.5 Ω/, N + depth 15 μm).
Next, as shown in Figure C, this was heated to a temperature of 1270℃.
The highly concentrated impurity layer 2 is placed in a diffusion furnace for 270 hours and slumped to obtain a highly concentrated impurity layer 3 having a diffusion depth of 190 μm. Next, as shown in figure D,
Remove the high concentration impurity layer 3 on one side by scraping up to 220 μm from the surface using #1000 lap. Furthermore, mirror wrapping is performed to remove the crushed layer on the surface of the high concentration impurity layer 3 and give the surface a mirror finish, and as shown in Fig. A semiconductor substrate 5 having a mirror finish on the surface of 250 μm is obtained. However, the conventional semiconductor substrate manufacturing method has the following drawbacks. In order to manufacture a semiconductor substrate 5 with a finished thickness of 250 μm, a thick semiconductor substrate 1 having an inner thickness of 500 μm is required, and a large amount of the semiconductor substrate 1 is lost. The amount of scraping on one side must be at least 200μm,
Since mirror lap finishing and mechanical finishing are required after polishing with #1000 lap, the lifetime of the substrate will be shortened when making power semiconductor devices. The present invention has been made in view of this point, and has discovered a method for manufacturing a semiconductor substrate that can easily manufacture a semiconductor substrate with a long lifetime using a thin semiconductor. An embodiment of the present invention will be described above with reference to the drawings. First, as shown in Figure 2A, the thickness
An N conductivity type semiconductor substrate 10 with a 270 μm #1000 wrap finish is prepared. Next, as shown in FIG .
The film is deposited in an oxidizing atmosphere at a temperature of 3 hours to form a highly concentrated impurity layer 11 (sheet resistance 0.3 to 0.5 Ω/□ diffusion depth 15 μm). Next, as shown in FIG. 3C, oxidation is performed at a temperature of 1000° C. for 2 minutes while flowing steam to form a first oxide film 12 on the surface of the high concentration impurity layer 11. This first oxide film 12 is
High concentration impurity layer 1 in the next N + slumping diffusion
The film thickness is preferably set to 8000 Å to 10000 Å. Next, after protecting the back surface with wax or the like, the first oxide film 12 on one surface is removed using a hydrofluoric acid solution. Furthermore, chemical etching is applied to the removed surface. In this case, the etched finished surface needs to be a mirror finished surface because there is an oxide film etching step using a photonist in the semiconductor device manufacturing process. In addition, the semiconductor substrate 10
This is done so that the inside is uniform and the high concentration impurity layer 11 on one side can be removed reliably. For example, using a mixed acid etching solution with a volume ratio of hydrofluoric acid: nitric acid: acetic acid = 1:2:1, etching is performed for 200 seconds at a solution temperature of 15° C. to obtain an etching amount of 30 μm. Thereafter, as shown in Figure D, the protective wax on the back surface is removed by triclean treatment. Next, as shown in Figure E, a second oxide film 13 is formed on the mirror-etched surface. The second oxide film 13 is, for example,
The film is formed by oxidation in a steam atmosphere at 1000° C. for 4 hours, and the film thickness is 10000 to 11000 Å. Next, as shown in FIG. 3, the first oxide film 12,
A large number of semiconductor substrates 10 each having a high concentration impurity layer 11 and a second oxide film 13 formed thereon are prepared.
The stack 15 is assembled by abutting the oxide films 12 and the second oxide films 13 back to back so that they overlap and fixing them together while applying pressure with the guide plate 14 so that no gaps are left. 50 between guide plates 14
~100 semiconductor substrates 10 are provided back to back. Next, this stack 15 was placed in an oxidizing atmosphere at 1270°C for 270 hours to form a highly concentrated impurity layer 1.
Stack diffusion is performed until the diffusion depth of 1 reaches 190 μm. After the stack diffusion, the semiconductor substrates 10 that are stuck together in a back-to-back state are immersed in a hydrofluoric acid solution.
The first oxide film 12 and the second oxide film 13 are dissolved and removed to obtain a semiconductor substrate 16 whose surface is finished by mirror etching, as shown in FIG. 2F. As described above, according to this semiconductor substrate manufacturing method, it is possible to easily obtain the semiconductor substrate 16 whose surface is finished by chemical mirror etching using the thin semiconductor substrate 10. Further, the first oxide film 12 was attached to the surface of the high concentration impurity layer 11 before etching one side, the second oxide film 13 was attached to the exposed surface after etching one side, and the number of semiconductor substrates 10 The first oxide film 1
By stacking the high concentration impurity layer 11 and the second oxide film 13 back to back and bringing them into close contact with each other while applying pressure with the guide plate 14, the high concentration impurity layer 11 is stacked and diffused as shown in FIG. The impurities in the concentrated impurity layer 11 are diffused to the outside to form the semiconductor substrate 10.
Formation of high concentration impurity region 16a therein can be prevented. Furthermore, the high concentration impurity layer 11
Because there is no need to scrape off more than 200μm on one side after the stack is diffused, 30μm can be removed without wrapping.
A mirror surface can be formed by single-sided chemical etching of about m. Also, since a mirror surface can be formed by chemical etching, fracture and strain layers can be reduced compared to conventional mechanical surface finishing methods. As a result, as shown in FIG. 5, it is possible to manufacture a semiconductor device 18 in which an impurity region 17 forming a PN junction with a planar structure is formed at a depth of 30 to 40 μm from the surface and an electrode is provided. The lifetime distribution of this semiconductor substrate 16 is as shown in FIG. 6B, which is much longer than the lifetime distribution diagram of a semiconductor substrate manufactured by the conventional method shown in FIG. 6A. Although the embodiments have been described with reference to an NPN type semiconductor substrate, the present invention can of course be similarly applied to a PNP type semiconductor substrate. As explained above, according to the method for manufacturing a semiconductor substrate according to the present invention, a semiconductor substrate with a long lifetime can be easily manufactured using a thin semiconductor substrate.

【図面の簡単な説明】[Brief explanation of drawings]

第1図A乃至同図Eは、従来の半導体基板の製
造工程図を示す説明図、第2図A乃至同図Fは、
本発明の半導体基板の製造工程図を示す説明図、
第3図は、スタツク拡散の状態を示す説明図、第
4図は、N+拡散時の裏面からのN+不純物の飛出
しによるN-面での異状拡散を示す説明図、第5
図は、本発明にて製造された半導体基板を使用し
た半導体装置の断面図、第6図Aは、従来法で製
造された半導体基板のライフタイムの分布図、第
6図Bは、本発明にて製造された半導体基板のラ
イフタイムの分布図を示す。 10……半導体基体、11……高濃度不純物
層、12……第1酸化膜、13……第2酸化膜、
14……ガイド板、16……半導体基板。
1A to 1E are explanatory diagrams showing conventional semiconductor substrate manufacturing process diagrams, and FIGS. 2A to 2F are
An explanatory diagram showing a manufacturing process diagram of the semiconductor substrate of the present invention,
Fig. 3 is an explanatory diagram showing the state of stack diffusion, Fig. 4 is an explanatory diagram showing abnormal diffusion on the N - plane due to the jumping out of the N + impurity from the back surface during N + diffusion, and Fig. 5 is an explanatory diagram showing the state of stack diffusion.
The figure is a cross-sectional view of a semiconductor device using a semiconductor substrate manufactured by the present invention, Figure 6A is a lifetime distribution diagram of a semiconductor substrate manufactured by a conventional method, and Figure 6B is a diagram of a semiconductor device manufactured by the present invention The lifetime distribution diagram of semiconductor substrates manufactured in 10... Semiconductor base, 11... High concentration impurity layer, 12... First oxide film, 13... Second oxide film,
14...Guide plate, 16...Semiconductor substrate.

Claims (1)

【特許請求の範囲】[Claims] 1 少なくとも2枚の1導電型の半導体基体の
夫々の両面に同導電型の高濃度不純物層を形成す
る工程と、該高濃度不純物層の表面に第1酸化膜
を形成する工程と、片面側の前記高濃度不純物層
及び該第1酸化膜を化学エツチングにて除去しそ
の露出表面にミラーエツチング仕上げを施す工程
と、前記ミラーエツチング仕上げされた表面に第
2酸化膜を形成する工程と、一方の前記半導体基
体の該第1酸化膜と他方の前記半導体基体の該第
1酸化膜とを突合せた状態で、もしくは一方の前
記半導体基体の該第2酸化膜と他方の前記半導体
基体の該第2酸化膜とを突合せた状態で酸素雰囲
気中の加熱状態で前記半導体基体と同導電型の不
純物を導入して半導体内にスランピング層を形成
する工程と、他面の第1酸化膜を除去する工程と
を具備することを特徴とする半導体基板の製造方
法。
1. A step of forming a high concentration impurity layer of the same conductivity type on both surfaces of each of at least two semiconductor substrates of one conductivity type, a step of forming a first oxide film on the surface of the high concentration impurity layer, and a step of forming a first oxide film on the surface of the high concentration impurity layer; a step of removing the high concentration impurity layer and the first oxide film by chemical etching and applying a mirror etching finish to the exposed surface; a step of forming a second oxide film on the mirror etching finished surface; the first oxide film of the semiconductor substrate and the first oxide film of the other semiconductor substrate, or the second oxide film of one of the semiconductor substrates and the first oxide film of the other semiconductor substrate. a step of forming a slumping layer in the semiconductor by introducing an impurity of the same conductivity type as the semiconductor substrate under heating in an oxygen atmosphere with the two oxide films butted against each other; and removing the first oxide film on the other side. A method for manufacturing a semiconductor substrate, comprising the steps of:
JP15993580A 1980-11-13 1980-11-13 Manufacture of semiconductor substrate Granted JPS5784171A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15993580A JPS5784171A (en) 1980-11-13 1980-11-13 Manufacture of semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15993580A JPS5784171A (en) 1980-11-13 1980-11-13 Manufacture of semiconductor substrate

Publications (2)

Publication Number Publication Date
JPS5784171A JPS5784171A (en) 1982-05-26
JPS641066B2 true JPS641066B2 (en) 1989-01-10

Family

ID=15704363

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15993580A Granted JPS5784171A (en) 1980-11-13 1980-11-13 Manufacture of semiconductor substrate

Country Status (1)

Country Link
JP (1) JPS5784171A (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5313921B2 (en) * 1971-09-23 1978-05-13
JPS5123073A (en) * 1974-08-21 1976-02-24 Hitachi Ltd Handotaisochino seizoho
JPS5941030B2 (en) * 1976-08-30 1984-10-04 株式会社東芝 Hydroelectric power plant output limiting device
JPS54119883A (en) * 1978-03-10 1979-09-18 Hitachi Ltd Manufacture for semiconductor device

Also Published As

Publication number Publication date
JPS5784171A (en) 1982-05-26

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