JPH0235459B2 - - Google Patents

Info

Publication number
JPH0235459B2
JPH0235459B2 JP56181807A JP18180781A JPH0235459B2 JP H0235459 B2 JPH0235459 B2 JP H0235459B2 JP 56181807 A JP56181807 A JP 56181807A JP 18180781 A JP18180781 A JP 18180781A JP H0235459 B2 JPH0235459 B2 JP H0235459B2
Authority
JP
Japan
Prior art keywords
substrate
layer
substrates
slumping
bonded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56181807A
Other languages
Japanese (ja)
Other versions
JPS5884458A (en
Inventor
Shoichi Kitane
Shigeru Pponjo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP18180781A priority Critical patent/JPS5884458A/en
Publication of JPS5884458A publication Critical patent/JPS5884458A/en
Publication of JPH0235459B2 publication Critical patent/JPH0235459B2/ja
Granted legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)

Description

【発明の詳細な説明】 本発明は半導体基板の製造方法に関し、特に電
力用パワートランジスタの製造に用いる半導体基
板の製造方法に係る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor substrate, and particularly to a method for manufacturing a semiconductor substrate used for manufacturing a power transistor for electric power.

電力用パワートランジスタの製造には、一導電
型の半導体基板の裏面側に基板と同導電型の高濃
度不純物層を形成した二層構造(NonN+または
PonP+)の半導体基板が用いられる。これは、電
力用パワートランジスタでは基板の裏面側からコ
レクタ電極を取り出すことから、コレクタの飽和
抵抗を減少させる上で基板の裏面側に高濃度不純
物層が必要とされるためである。上記二層構造を
有する半導体基板の従来の製造方法を、npnバイ
ポーラ型パワートランジスタの製造に用いる
NonN+型のシリコン基板を例に説明すれば次の
通りである。
To manufacture power transistors for electric power, a two-layer structure (NonN + or
A PonP + ) semiconductor substrate is used. This is because in a power transistor for electric power, the collector electrode is taken out from the back side of the substrate, so a high concentration impurity layer is required on the back side of the substrate in order to reduce the saturation resistance of the collector. The conventional manufacturing method for a semiconductor substrate having the above two-layer structure is used to manufacture an NPN bipolar power transistor.
The following is an explanation using a NonN + type silicon substrate as an example.

(i) まず、厚さ500μ、#1000ラツプ仕上げ面を
有するn-型シリコン基板1にオキシ塩化燐
(POCl3)を拡散源として1200℃、3時間の燐
拡散を行ない、基板1の両面に拡散深度15μ、
表面の不純物濃度4〜6×1021/cm3のn+型デポ
ジシヨン層2を形成する(第1図a図示)。
(i) First, phosphorus was diffused at 1200°C for 3 hours using phosphorus oxychloride (POCl 3 ) as a diffusion source on an n - type silicon substrate 1 with a thickness of 500μ and a #1000 lap finish, and then diffused phosphorus on both sides of the substrate 1. Diffusion depth 15μ,
An n + type deposition layer 2 having a surface impurity concentration of 4 to 6×10 21 /cm 3 is formed (as shown in FIG. 1A).

(ii) 次に、1270℃、270時間の熱処理によりn+
デポジシヨン層2のスランピングを行ない、拡
散深度190μ、不純物表面濃度1×1020/cm3以上
のn+型スランピング層3を形成する(同図b
図示)。
(ii) Next, the n + type deposition layer 2 is slumped by heat treatment at 1270°C for 270 hours to form an n + type slumping layer 3 with a diffusion depth of 190 μ and an impurity surface concentration of 1 × 10 20 /cm 3 or more. (Figure b
(Illustrated).

(iii) 次に、#1000ラツピングにより一方のスラン
ピング層3の表面から220μだけ削除する。こ
れにより、n-型層1も220μ−190μ=30μだけ削
除され、従つて、ラツピングされなかつたn+
型のスランピング層3上にn-型層1を有する
NonN+型のシリコン基板が得られる(同図c
図示)。
(iii) Next, remove 220μ from the surface of one slumping layer 3 by #1000 wrapping. This also removes n - type layer 1 by 220μ - 190μ = 30μ, so that the unwrapped n +
having an n - type layer 1 on the slumping layer 3 of the mold
A NonN + type silicon substrate is obtained (Fig.
(Illustrated).

このときn-型層1表面は#1000ラツピング
面4になつている。
At this time, the surface of the n - type layer 1 becomes a #1000 wrapping surface 4.

(iv) 次に、n-層1の表面をミラーラツピングす
ることより、ラツピング面4の破砕層を除去す
ると共に表面をミラー面5に仕上げる。これに
より裏面側にコレクタ電極を形成するための深
さ190μのn+型スランピング層3と、その上に
コレクタ領域となる厚さ60μのn-型領域1を有
し、全体の厚さが250μのNonN+型シリコン基
板が得られる(同図d図示)。
(iv) Next, by mirror wrapping the surface of the n - layer 1, the crushed layer on the wrapping surface 4 is removed and the surface is finished into a mirror surface 5. As a result, there is an n + type slumping layer 3 with a depth of 190μ for forming the collector electrode on the back side, and an n - type region 1 with a thickness of 60μ that will become the collector region on top of it, and the total thickness is 250μ. A NonN + type silicon substrate is obtained (as shown in figure d).

こうして得られた二層構造の半導体基板は、そ
の製造方法に因んでOSL基板(One Side mirror
Lapping基板)と呼ばれている。
The two-layer semiconductor substrate obtained in this way is an OSL substrate (One Side Mirror) due to its manufacturing method.
Lapping board).

ところで、上記従来の製造方法では、厚さ
250μのOSL基板を得るために略2倍の厚さの基
板から出発しなければならず、材料ロスが大きい
という問題があつた。また、片側を220μもラツ
ピングして削除しなければならないため長時間の
ラツピングを要すること、および高濃度のラツピ
ングを行なうために高度の技術を要することなど
からコスト高になるという問題があつた。更に、
削除方法が#1000ラツピングであること、および
その後のミラー面仕上げも機械的なラツピング仕
上げであることから、上記従来の製造方法による
OSL基板を用いて作成された素子では少数キヤ
リアのライフタイムが低下するという問題があつ
た。
By the way, in the above conventional manufacturing method, the thickness
In order to obtain a 250μ OSL substrate, it was necessary to start from a substrate that was approximately twice as thick, resulting in a problem of large material loss. In addition, there were problems in that it required a long wrapping time to wrap and remove 220μ on one side, and that high-density wrapping required sophisticated technology, resulting in high costs. Furthermore,
The removal method is #1000 wrapping, and the subsequent mirror surface finishing is also mechanical wrapping, so it is not possible to use the above conventional manufacturing method.
Devices fabricated using OSL substrates have had the problem of reduced minority carrier lifetime.

本発明は上述の事情に鑑みてなされたもので、
従来と同様の厚さを有する二層構造の半導体基板
を従来よりも薄い基板から出発して低コストかつ
高い材料効率で製造することができ、しかも少数
キヤリアの高いライフタイムを得ることのできる
半導体基板の製造方法を提供するものである。
The present invention was made in view of the above circumstances, and
A semiconductor that can manufacture a two-layer structure semiconductor substrate with the same thickness as a conventional one starting from a thinner substrate at low cost and with high material efficiency, and also has a high minority carrier lifetime. A method for manufacturing a substrate is provided.

即ち、本発明は不純物濃度の低い一導電型の半
導体基板の両面に酸化膜を形成する工程と、該基
板の片面側の酸化膜上に液状シリカ化合物を塗布
し、該液状シリカ化合物を介して二枚の基板を密
に固着した貼着体を形成する工程と、該貼着体に
不純物拡散を行なうことにより基板の非固着面側
に基板と同導電型の高濃度不純物層を形成する工
程と、貼着体全面を酸化することにより基板の非
固着面側に酸化膜を成長させる工程と、多数の貼
着体を積層加圧したスタツク状態で前記高濃度不
純物層のシランピングを行なつた後、このスタツ
ク状態から個々の基板を分離する工程と、該分離
された基板の非スランピング面をミラーエツチン
グ仕上げする工程とからなる半導体基板の製造方
法である。
That is, the present invention includes a step of forming an oxide film on both sides of a semiconductor substrate of one conductivity type with a low impurity concentration, applying a liquid silica compound on the oxide film on one side of the substrate, and applying a liquid silica compound to the oxide film on one side of the substrate. A process of forming a bonded body in which two substrates are closely bonded together, and a process of forming a highly concentrated impurity layer of the same conductivity type as the substrate on the non-bonded side of the substrate by diffusing impurities into the bonded body. , a step of growing an oxide film on the non-bonded surface side of the substrate by oxidizing the entire surface of the adhered body, and silamping of the high concentration impurity layer in a stacked state in which a large number of adhered bodies were laminated and pressurized. Thereafter, the method for manufacturing semiconductor substrates comprises the steps of separating individual substrates from this stacked state, and finishing the non-slumping surfaces of the separated substrates by mirror etching.

以下、第2図a〜gを参照して本発明をnpnバ
イポーラ型パワートランジスタ用シリコン基板の
製造に適用した一実施例を説明する。
Hereinafter, an embodiment in which the present invention is applied to the manufacture of a silicon substrate for an NPN bipolar power transistor will be described with reference to FIGS. 2a to 2g.

実施例 (i) まず、厚さ270μ、#1000ラツプ仕上げのn-
型シリコン基板11を1000℃のドライ酸素雰囲
気中で20分間熱処理することにより、その両側
表面に膜厚500〜700Åの熱酸化膜12を形成す
る(第2図a図示)。
Example (i) First, 270μ thick, #1000 lap finished n-
By heat-treating the mold silicon substrate 11 in a dry oxygen atmosphere at 1000 DEG C. for 20 minutes, thermal oxide films 12 having a thickness of 500 to 700 Å are formed on both surfaces thereof (as shown in FIG. 2A).

(ii) 次に、基板11の片面の熱酸化膜12上に液
状のシリカ化合物溶液をスピンナー等によつ
て、例えば2000rpm、15秒間の条件で塗布形成
し、この液状シリカ化合膜13を介して二枚の
同様の基板を貼り合わせる。続いて、1000℃以
上の酸素雰囲気中で熱処理を行なつて液状シリ
カ化合物膜を固化することにより二枚の基板1
1,11′をシリカ化合物層13を介して密着
固定する(第2図b図示)。
(ii) Next, a liquid silica compound solution is applied onto the thermal oxide film 12 on one side of the substrate 11 using a spinner or the like, for example, at 2000 rpm for 15 seconds. Attach two similar boards together. Next, the liquid silica compound film is solidified by heat treatment in an oxygen atmosphere at 1000°C or higher, thereby forming the two substrates 1.
1 and 11' are closely fixed through the silica compound layer 13 (as shown in FIG. 2b).

なお、この熱処理により基板11,11′の
表面に先に形成されていた熱酸化膜12,1
2′がシリカ化合物13と反応して強固な接合
が達成される。
Note that this heat treatment removes the thermal oxide films 12, 1 previously formed on the surfaces of the substrates 11, 11'.
2' reacts with the silica compound 13 to achieve a strong bond.

(iii) 次に、例えばオキシ塩化燐を拡散源として
1200℃の酸化性雰囲気中で3時間程度の燐拡散
を行ない、拡散深度15μ、不純物表面濃度4
〜6×1021/cm3のn+型高濃度不純物層14,1
4′を形成する(第2図e図示)。
(iii) Next, use e.g. phosphorus oxychloride as a diffusion source.
Phosphorus was diffused for about 3 hours in an oxidizing atmosphere at 1200℃, with a diffusion depth of 15μ and an impurity surface concentration of 4.
~6×10 21 /cm 3 n + type high concentration impurity layer 14,1
4' (as shown in Figure 2e).

(iv) 次に、スチーム雰囲気下で1000℃、4時間の
酸化を行ない、1.0〜1.2μの酸化膜15,1
5′を成長させる(第2図d図示)。
(iv) Next, oxidation was performed at 1000℃ for 4 hours in a steam atmosphere to form an oxide film 15,1 with a thickness of 1.0 to 1.2μ.
5' (as shown in Figure 2d).

(v) 次に、第2図dのように二枚の基板11,1
1′を密着したものを1270℃のN2/O2=2/1
の混合ガラス奮囲気下で270時間のスランピン
グを行ない、拡散深度190μ、不純物表面濃度
1×1020/cm3以上のn+型スランピング層16,
16′を形成する(第2図e図示)。
(v) Next, as shown in Fig. 2d, two substrates 11, 1
1′ in close contact with 1270℃ N 2 /O 2 = 2/1
Slumping was performed for 270 hours under a mixed glass atmosphere of 100 mL of mixed glass, and an n + type slumping layer 16 with a diffusion depth of 190 μ and an impurity surface concentration of 1×10 20 /cm 3 or more was formed.
16' (as shown in FIG. 2e).

このときのスランピングは、第3図に示すよ
うに、石英ガイド板100により第2図dのよう
に基板11,11′を密着結合したものを相互
に隙間のないように多数重ね合わせて完全スタ
ツク状態とし、これを石英拡散ボート101に
載せて行なう。
In this slumping, as shown in FIG. 3, the substrates 11 and 11' are tightly bonded as shown in FIG. This is carried out on a quartz diffusion boat 101.

(vi) 上記スランピングの終了後、第3図の完全ス
タツク状の基板11,11′は酸化膜15およ
びシリカ化合物層13を介して相互に密着結合
されているから、これをフツ酸液中に浸漬する
ことにより個々の基板に分離する(第2図f図
示)。
(vi) After the above-mentioned slumping is completed, the completely stacked substrates 11 and 11' shown in FIG. The substrates are separated into individual substrates by dipping (as shown in FIG. 2f).

(vii) 次に、分離された個々の基板におけるn-
層11の表面を例えばフツ酸、硝酸および酢酸
の混合液(HF:HNO3:CH3COOH=1:
3:2)で20μ程度エツチングすることにより
ミラー面仕上げを行なう(第2図g図示)。
(vii) Next, the surface of the n - type layer 11 on each separated substrate is coated with, for example, a mixed solution of hydrofluoric acid, nitric acid, and acetic acid (HF:HNO 3 :CH 3 COOH=1:
3:2) to a mirror surface finish by etching about 20μ (as shown in Figure 2g).

こうして、拡散深さ190μのスランピング層1
6と膜厚60μのn-型層11とからなり、全体が
250μの厚さを有する二層構造のNonN+型シリコ
ン基板が製造される。なお、このように片面をエ
ツチングによりミラー仕上げされた半導体基板の
ことをOSL基板に対してOSE基板(One Side
mirror Etching基板)と呼ぶことにする。
In this way, the slumping layer 1 with a diffusion depth of 190μ
6 and an n - type layer 11 with a film thickness of 60μ, the entire structure is
A double-layered NonN + type silicon substrate with a thickness of 250μ is fabricated. Note that a semiconductor substrate that has one side mirror-finished by etching is called an OSE substrate (one side substrate) as opposed to an OSL substrate.
We will call it mirror etching board).

上記実施例によれば、出発基板11の片面にの
みn+型スランピング層16を形成できることか
ら、厚さ250μのOSE基板を製造するに際して厚
さ270μの原料基板を用いればよい。従つて、従
来の製造方法に比較して原料ロスが著しく小さく
なり、材料効率を飛躍的に向上することができ
る。また、ミラー面仕上げに際しても、n-型層
11を20μ程度除去すればよいことからエツチン
グによるミラー面仕上げを用いることができる。
従つて、ミラー面仕上げの工程が従来のラツピン
グによる場合に比較して極めて容易かつ短時間で
済むからコストの低減が可能となる一方、機械的
なラツピングを行なう必要がないからn-型層1
1の破砕層や歪が減少し、従来の製造方法に比較
して少数キヤリアのライフタイムを向上すること
がきる。因みに、従来のOSL基板と上記実施例
のOSE基板の両方を用いてその表面から30〜40μ
の深さにプレーナー構造のPN接合を形成し、電
極を形成してライフタイムを測定した結果を第4
図に示す。同図Aは従来のOSL基板を用いた場
合のライフタイムの分布図であり、同図Bは上記
実施例のOSE基板を用いた場合のライフタイム
の分布図である。この結果は上記実施例による
OSE基板の方が少数キヤリアのライフタイムが
長長いことを示している。
According to the above embodiment, since the n + type slumping layer 16 can be formed only on one side of the starting substrate 11, a raw material substrate with a thickness of 270 μm may be used when manufacturing an OSE substrate with a thickness of 250 μm. Therefore, compared to conventional manufacturing methods, raw material loss is significantly reduced, and material efficiency can be dramatically improved. Also, when finishing the mirror surface, it is possible to use etching to finish the mirror surface since it is sufficient to remove about 20 μm of the n - type layer 11.
Therefore, the mirror surface finishing process is extremely easy and takes a shorter time than conventional wrapping, which makes it possible to reduce costs, while there is no need to mechanically wrap the n - type layer 1.
The fracture layer and strain of 1 are reduced, and the lifetime of minority carriers can be improved compared to conventional manufacturing methods. By the way, when using both the conventional OSL substrate and the OSE substrate of the above example,
A planar structure PN junction was formed at the depth of , electrodes were formed, and the lifetime was measured.
As shown in the figure. Figure A is a lifetime distribution chart when the conventional OSL board is used, and Figure B is a lifetime distribution diagram when the OSE board of the above embodiment is used. This result is based on the above example.
This shows that the OSE board has a longer minority carrier lifetime.

その他、出発基板の片方側にのみ高濃度のスラ
ンピング層を形成する方法は従来も一部行なわれ
てはいたが、この方法においては第5図に示すよ
うに片面側に高濃度のスランピングを行なう際
に、n+層の表面から飛び出したn型不純物がn-
層の表面に侵入するのを避けることができず、そ
のためにn-層の膜厚制御が不安定になるという
問題があつた。これに対して上記実施例の方法に
よればそのような問題を完全に解決できることは
明らかである。
In addition, some methods have been used in the past in which a highly concentrated slumping layer is formed on only one side of the starting substrate, but in this method, as shown in Figure 5, highly concentrated slumping is performed on one side. At this time, the n-type impurity that jumped out from the surface of the n + layer becomes n -
There was a problem in that it was impossible to avoid penetrating into the surface of the layer, and as a result, the control of the thickness of the n - layer became unstable. On the other hand, it is clear that the method of the above embodiment can completely solve this problem.

なお、本発明はNonN+型の半導体基板のみな
らず、PonP型の半導体基板の製造にも適用でき
ることは言うまでもない。
It goes without saying that the present invention can be applied not only to the production of NonN + type semiconductor substrates but also to the production of PonP type semiconductor substrates.

以上詳述したように、本発明によれば高い材料
効率および低コストで電力用パワートランジスタ
の製造に用いる二層構造の半導体基板を製造する
ことができ、しかも優れた少数キヤリアのライフ
タイム特性を得ることができる半導体基板の製造
方法を提供できるものである。
As described in detail above, according to the present invention, it is possible to manufacture a two-layer structure semiconductor substrate for use in manufacturing power transistors with high material efficiency and low cost, and also to have excellent minority carrier lifetime characteristics. It is possible to provide a method for manufacturing a semiconductor substrate that can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図a〜dは従来のOSL基板の製造工程を
示す断面図、第2図a〜gは本発明の一実施例に
なる半導体基板の製造工程を示す断面図、第3図
は第2図eの工程を行なう態様を示す説明図、第
4図は従来のOSL基板と本発明の一実施例によ
り製造されたOSE基板における少数キヤリアの
ライフタイム特性を比較して示す分布図、第5図
は第1図a〜dの従来例以外に従来行なわれてい
た製造方法の問題点を示す説明図である。 11,11′……n-型シリコン基板、12,1
2′……熱酸化膜、13……シリカ化合物層、1
4,14′……n+型高濃度不純物層、15,1
5′……酸化膜、16,16′……n+型スランピ
ング層、100……石英ガイド板、101……石
英ボート。
1A to 1D are cross-sectional views showing the manufacturing process of a conventional OSL substrate, FIGS. 2A to 2G are cross-sectional views showing the manufacturing process of a semiconductor substrate according to an embodiment of the present invention, and FIG. FIG. 4 is a distribution diagram showing a comparison of the lifetime characteristics of minority carriers in a conventional OSL board and an OSE board manufactured according to an embodiment of the present invention. The figure is an explanatory diagram showing problems in conventional manufacturing methods other than the conventional examples shown in FIGS. 1a to 1d. 11,11'...n - type silicon substrate, 12,1
2'...Thermal oxide film, 13...Silica compound layer, 1
4,14'...n + type high concentration impurity layer, 15,1
5'...Oxide film, 16,16'...n + type slumping layer, 100...Quartz guide plate, 101...Quartz boat.

Claims (1)

【特許請求の範囲】[Claims] 1 不純物濃度の低い一導電型の半導体基板の両
面に酸化膜を形成する工程と、該基板の片面側の
酸化膜上に液状シリカ化合物を塗布し、該液状シ
リカ化合物を介して二枚の基板を密に固着した貼
着体を形成する工程と、該貼着体に不純物拡散を
行なうことにより基板の非固着面側に基板と同導
電型の高濃度不純物層を形成する工程と、貼着体
全面を酸化することにより基板の非固着面側に酸
化膜を成長させる工程と、多数の貼着体を積層加
圧したスタツク状態で前記高濃度不純物層のスラ
ンピングを行なつた後、このスタツク状態から
個々の基板を分離する工程と、該分離された基板
の非スランピング面をミラーエツチング仕上げす
る工程とからなる半導体基板の製造方法。
1. A step of forming an oxide film on both sides of a semiconductor substrate of one conductivity type with a low impurity concentration, and applying a liquid silica compound on the oxide film on one side of the substrate, and bonding the two substrates through the liquid silica compound. a step of forming a bonded body in which the bonded body is tightly adhered; a step of forming a highly concentrated impurity layer of the same conductivity type as the substrate on the non-bonded side of the substrate by diffusing impurities into the bonded body; After a process of growing an oxide film on the non-bonded side of the substrate by oxidizing the entire surface of the substrate, and slumping the high concentration impurity layer in a stacked state in which a large number of bonded bodies are laminated and pressurized, this stack is 1. A method for manufacturing a semiconductor substrate, comprising the steps of separating individual substrates from a state, and finishing a non-slumping surface of the separated substrates by mirror etching.
JP18180781A 1981-11-13 1981-11-13 Manufacture of semiconductor substrate Granted JPS5884458A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18180781A JPS5884458A (en) 1981-11-13 1981-11-13 Manufacture of semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18180781A JPS5884458A (en) 1981-11-13 1981-11-13 Manufacture of semiconductor substrate

Publications (2)

Publication Number Publication Date
JPS5884458A JPS5884458A (en) 1983-05-20
JPH0235459B2 true JPH0235459B2 (en) 1990-08-10

Family

ID=16107182

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18180781A Granted JPS5884458A (en) 1981-11-13 1981-11-13 Manufacture of semiconductor substrate

Country Status (1)

Country Link
JP (1) JPS5884458A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL8501773A (en) * 1985-06-20 1987-01-16 Philips Nv METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4964370A (en) * 1972-06-21 1974-06-21
JPS5441665A (en) * 1977-09-09 1979-04-03 Mitsubishi Electric Corp Manufacture for semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4964370A (en) * 1972-06-21 1974-06-21
JPS5441665A (en) * 1977-09-09 1979-04-03 Mitsubishi Electric Corp Manufacture for semiconductor device

Also Published As

Publication number Publication date
JPS5884458A (en) 1983-05-20

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