JPS63205926A - Manufacture of dielectric isolation substrate - Google Patents
Manufacture of dielectric isolation substrateInfo
- Publication number
- JPS63205926A JPS63205926A JP3979287A JP3979287A JPS63205926A JP S63205926 A JPS63205926 A JP S63205926A JP 3979287 A JP3979287 A JP 3979287A JP 3979287 A JP3979287 A JP 3979287A JP S63205926 A JPS63205926 A JP S63205926A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- silicon
- polycrystalline silicon
- crystal silicon
- dielectric isolation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 49
- 238000002955 isolation Methods 0.000 title claims description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 26
- 238000010438 heat treatment Methods 0.000 claims abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 36
- 238000000034 method Methods 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 11
- 229910052710 silicon Inorganic materials 0.000 abstract description 11
- 239000010703 silicon Substances 0.000 abstract description 11
- 125000004430 oxygen atom Chemical group O* 0.000 abstract description 2
- 230000001590 oxidative effect Effects 0.000 abstract 4
- 238000000151 deposition Methods 0.000 description 8
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Landscapes
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発明は誘電体分離基板を安価に製造する製造法に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a manufacturing method for manufacturing a dielectric isolation substrate at low cost.
酸化膜のような誘電体で素子と素子を分離したＬ８Ｉは
高耐圧な特性を有している。誘電体で素子間を分離した
ＸＪｓｘ基板を誘電体分離基板と呼んでいる。第３図に
従来の誘電体分離基板の構成を示す。１は単結晶シリコ
ン基板、２はＶ溝、３は酸化膜、４は素子、５は多結晶
シリコンである。単結晶シリコン基板１はＶ ｎ ２と
酸化膜３で囲まれた、単結晶シリコン島に分割されてい
る。その製゛・遣方法は、（１）単結晶シリコン基板１
に異方性エツチングによシｖ形状のＶ溝２を設け％（２
）Ｖ溝２を設けた側に熱酸化によυ酸化膜３ｔ−付着さ
せる。L8I, in which elements are separated by a dielectric such as an oxide film, has a high breakdown voltage characteristic. An XJsx substrate in which elements are separated by a dielectric is called a dielectric isolation substrate. FIG. 3 shows the structure of a conventional dielectric isolation substrate. 1 is a single crystal silicon substrate, 2 is a V-groove, 3 is an oxide film, 4 is an element, and 5 is polycrystalline silicon. A single crystal silicon substrate 1 is divided into single crystal silicon islands surrounded by V n 2 and an oxide film 3 . The method for manufacturing and using it is as follows: (1) Single crystal silicon substrate 1
A V-shaped groove 2 is formed by anisotropic etching.
) A υ oxide film 3t is deposited on the side where the V groove 2 is provided by thermal oxidation.
（３）ｖ溝２を設けた側に多結晶シリコン５を堆積させ
、（４）Ｖ溝２を設けない側をＶ溝２の一部が現われる
まで研磨し、（５）研磨を施した単結晶シリコン基板１
の面に素子４を形成するプロセスとなっている。(3) Polycrystalline silicon 5 is deposited on the side where the V-groove 2 is provided, (4) the side where the V-groove 2 is not provided is polished until a part of the V-groove 2 appears, and (5) the polished unit is Crystalline silicon substrate 1
The process is to form the element 4 on the surface.
このような製造工程の中で最も時間と費用を要している
のは、多結晶シリコン５を堆積する工程である。ＣｖＤ
を用いて数百μｍの厚さまで多結晶シリコンを堆積しな
ければならないので、堆積に非常に時間を要する。また
、ＣｖＤ装置は非常に高価である。Of these manufacturing steps, the step that requires the most time and cost is the step of depositing polycrystalline silicon 5. CvD
Since polycrystalline silicon must be deposited to a thickness of several hundred μm using a method, the deposition process takes a very long time. Also, CvD devices are very expensive.
従って、多結晶シリコンの堆積が誘電体分離基板の価格
に占める割合は大きく、安価にする方法が種々検討され
ているがこれといったものがないのが現状である。Therefore, the deposition of polycrystalline silicon occupies a large proportion of the price of the dielectric isolation substrate, and although various methods to reduce the cost have been studied, there is currently no such method.
本発明の目的は誘電体分離基板における多結晶シリコン
の堆積厚さを薄くシ、安価な基板を提供するものである
。An object of the present invention is to reduce the thickness of polycrystalline silicon deposited on a dielectric isolation substrate and provide an inexpensive substrate.
〔問題点を解決するための手段及び発明の構成〕本発明
は誘電体分離基板の製造において■溝を埋める程度に薄
く多結晶シリコンを堆積し、支持、基板となる第２の単
結晶シリコン基板と堆積した多結晶シリコンとを接合す
ることにより多結晶シリコンを堆積する時間を短縮する
ことを最も主要外特徴とするものである。[Means for Solving the Problems and Structure of the Invention] In the production of a dielectric isolation substrate, the present invention consists of: ■ depositing polycrystalline silicon thin enough to fill the grooves, and depositing polycrystalline silicon on a second single-crystal silicon substrate to serve as a support and substrate; The most important feature is that the time for depositing polycrystalline silicon is shortened by bonding the deposited polycrystalline silicon and the deposited polycrystalline silicon.
従来の技術では多結晶シリコンを厚く堆積しなければな
らなかったのに対して、本発明の技術では薄く堆積すれ
ばよい点がことなるところである。The difference is that while the conventional technique required polycrystalline silicon to be deposited thickly, the technique of the present invention only needs to be deposited thinly.
（実施例１）
第１図は本発明の詳細な説明する図であって、１０は単
結晶シリコン基板に設けられたシリコン島、１１は酸化
膜、１２は素子、１３はＶ溝、１４は多結晶シリコン、
１５は薄い酸化膜、１６は支持単結晶シリコン基板、１
７は薄い酸化膜、である。本、実施例の誘電体分離基板
の製造は多結晶シリコン１４を堆積するまでは前述の従
来の製造法と同じであるが、堆積の厚さはＶ溝が埋まる
程度に堆積する。次に１多結晶シリコン１４の表面に薄
い酸化膜１５を付着させる。この多結晶シリコンと表面
に薄い酸化膜１７を有する支持単結晶シリコン基板１６
とを重ね合わせ、加熱すると多結晶シリコン１４と支持
単結晶シリコン基板１６は接合する。接合は薄い酸化膜
１５および１７の中の酸素原子が多結晶シリコン１４お
よび支持単結晶シリコン基板１６の中に拡散してゆき、
薄い酸化膜１５および１７が消失し、多結晶シリコン１
４と支持単結晶シリコン基板１６の清浄な面が現われ、
互いに接合する。このような接合は拡散接合と呼ばれて
いる。(Example 1) FIG. 1 is a diagram explaining the present invention in detail, in which 10 is a silicon island provided on a single crystal silicon substrate, 11 is an oxide film, 12 is an element, 13 is a V-groove, and 14 is a silicon island provided on a single crystal silicon substrate. polycrystalline silicon,
15 is a thin oxide film, 16 is a support single crystal silicon substrate, 1
7 is a thin oxide film. The manufacturing of the dielectric isolation substrate of this embodiment is the same as the conventional manufacturing method described above until the polycrystalline silicon 14 is deposited, but the thickness of the deposition is such that the V-groove is filled. Next, a thin oxide film 15 is deposited on the surface of the polycrystalline silicon 14. Support single crystal silicon substrate 16 having a thin oxide film 17 on the surface of this polycrystalline silicon
The polycrystalline silicon 14 and supporting single crystal silicon substrate 16 are bonded together by overlapping them and heating them. The bond is formed as oxygen atoms in the thin oxide films 15 and 17 diffuse into the polycrystalline silicon 14 and supporting single crystal silicon substrate 16.
Thin oxide films 15 and 17 disappear, and polycrystalline silicon 1
4 and the clean surface of the supporting single crystal silicon substrate 16 appear,
join each other. Such bonding is called diffusion bonding.
加熱温度と接合に必要な時間にはある種の関係があシ、
１３００℃で約２時間、９００℃で約２５０時間が必要
である。There is a certain relationship between the heating temperature and the time required for bonding.
Approximately 2 hours at 1300°C and approximately 250 hours at 900°C are required.
なお、薄い酸化膜１５および１７の厚さは出来る限シ薄
い方が接合に要する時間が短くなシ、効率が阜 Ｏ
良い。清浄な空気中に放置すると１０〜１００人の酸化
膜が出来るが、この位の薄さの膜の方がよい。Note that the thinner the thin oxide films 15 and 17, the shorter the time required for bonding and the higher the efficiency. If left in clean air, an oxide film of 10 to 100 layers will form, but a film as thin as this is better.
本発明の誘電体分離基板は上述のような構造となってい
るので多結晶シリコンを堆積する時間が短くてすみ、ま
た、多結晶シリコンに比べ単結晶シリコンは強度的に強
いので、強度の高い、信頼性のよい安価な基板を提供で
きる。Since the dielectric isolation substrate of the present invention has the above-mentioned structure, the time for depositing polycrystalline silicon is shortened, and since single-crystalline silicon is stronger than polycrystalline silicon, it has high strength. , it is possible to provide a reliable and inexpensive substrate.
（実施例２）
第２図は本発明の第２の実施例であって、艶は単結晶シ
リコン基板に設けられた単結晶シリコン島、２１はＶ溝
、ｎは酸化膜、羽は素子、冴は多結晶シリコン、５は支
持単結晶シリコン基板、である。本実施例の製造工程は
第１の実施例の場合と同じである。違いは多結晶シリコ
ン瀕をＶ溝２１の部分のみ堆積していることである。し
たがって、■溝２１に対応する支持単結晶シリコン基板
５の部分が接合している。このような構成とすれば、多
結晶シリコンの堆積時間をさらに短縮することができる
。(Example 2) FIG. 2 shows a second example of the present invention, in which the gloss is a single crystal silicon island provided on a single crystal silicon substrate, 21 is a V groove, n is an oxide film, wings are elements, Sae is polycrystalline silicon, and 5 is a supporting single crystal silicon substrate. The manufacturing process of this embodiment is the same as that of the first embodiment. The difference is that the polycrystalline silicon layer is deposited only in the V-groove 21. Therefore, the portion of the support single crystal silicon substrate 5 corresponding to the groove 21 is bonded. With such a configuration, the time for depositing polycrystalline silicon can be further shortened.
なお、実施例においては多結晶シリコンと単結晶シリコ
ン基板の接合を述べたが、多結晶シリコンと多結晶シリ
コン基板との接合も可能なことはいうまでもない。Although the embodiments have described bonding between polycrystalline silicon and single crystal silicon substrates, it goes without saying that bonding between polycrystalline silicon and polycrystalline silicon substrates is also possible.
〔発明の効果〕
以上説明したように、誘電体分離基板の製造において最
も長い処理時間を要し、費用も要しているＣＶＤによる
多結晶シリコンの堆積に対して、堆積量を少なくするこ
とで、処理時間を短縮することによシ安価な基板を提供
できる利点がある。[Effects of the Invention] As explained above, by reducing the amount of polycrystalline silicon deposited by CVD, which requires the longest processing time and costs the most in manufacturing dielectric isolation substrates, This method has the advantage of being able to provide inexpensive substrates by shortening the processing time.
第１図は、本発明の誘電体分離基板の断面図、第２図は
、本発明の誘電体分離基板の断面図、第３図は、従来の
誘電体分離基板の断面図を示す。
１・・・単結晶シリコン基板
２・・・Ｖ溝
３・・・酸化膜
４・・・素子
５・・・多結晶シリコン
１０・・・単結晶シリコン島
１１・・・酸化膜
１２・・・素子
１３・・・Ｖ溝
１４・・・多結晶シリコン
１５・・・薄い酸化膜
１６・・・支持単結晶シリコン基板
１７・・・薄い酸化膜
に・・・単結晶シリコン島
２１・・・Ｖ溝
ｎ・・・醸化膜
ｎ・・・素子
冴・・・多結晶シリコン
特許出願人 日本電信電話株式会社
代理人弁理士 玉 蟲 久 五 部（外２名）第１図
第２図
第３図FIG. 1 is a sectional view of a dielectric isolation substrate of the present invention, FIG. 2 is a sectional view of a dielectric isolation substrate of the invention, and FIG. 3 is a sectional view of a conventional dielectric isolation substrate. 1... Single crystal silicon substrate 2... V groove 3... Oxide film 4... Element 5... Polycrystalline silicon 10... Single crystal silicon island 11... Oxide film 12... Element 13...V groove 14...Polycrystalline silicon 15...Thin oxide film 16...Support single crystal silicon substrate 17...Thin oxide film...Single crystal silicon island 21...V Groove n...Fostering film n...Element Sae...Polycrystalline silicon patent applicant Nippon Telegraph and Telephone Corporation Representative Patent Attorney Hisashi Tamamushi Gobu (2 others) Figure 1 Figure 2 Figure 3 figure
Claims (2)
か一方、または、両方の基板に薄い酸化膜（１０〜５０
０Å）を付着させ、この多結晶シリコンとこの単結晶シ
リコン基板とを重ね合わせ、７００〜１４００℃の範囲
の温度で加熱することにより、この多結晶シリコンとこ
の単結晶シリコン基板とを接合することを特徴とする誘
電体分離基板の製造方法。(1) A thin oxide film (10 to 50%
0 Å), overlaying the polycrystalline silicon and the single-crystal silicon substrate, and heating the polycrystalline silicon and the single-crystal silicon substrate at a temperature in the range of 700 to 1400°C to bond the polycrystalline silicon and the single-crystal silicon substrate. A method for manufacturing a dielectric isolation substrate characterized by:
わせ、接合することを特徴とする特許請求の範囲第１項
記載の誘電体分離基板の製造方法。(2) A method for manufacturing a dielectrically isolated substrate according to claim 1, which comprises stacking and bonding polycrystalline silicon and polycrystalline silicon substrates.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3979287A JPS63205926A (en) | 1987-02-23 | 1987-02-23 | Manufacture of dielectric isolation substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3979287A JPS63205926A (en) | 1987-02-23 | 1987-02-23 | Manufacture of dielectric isolation substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63205926A true JPS63205926A (en) | 1988-08-25 |
Family
ID=12562803
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3979287A Pending JPS63205926A (en) | 1987-02-23 | 1987-02-23 | Manufacture of dielectric isolation substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63205926A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04336446A (en) * | 1991-05-13 | 1992-11-24 | Toshiba Corp | Using method for semiconductor device |
| US5313092A (en) * | 1989-05-12 | 1994-05-17 | Nippon Soken, Inc. | Semiconductor power device having walls of an inverted mesa shape to improve power handling capability |
| US5484738A (en) * | 1992-06-17 | 1996-01-16 | International Business Machines Corporation | Method of forming silicon on oxide semiconductor device structure for BiCMOS integrated circuits |
-
1987
- 1987-02-23 JP JP3979287A patent/JPS63205926A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5313092A (en) * | 1989-05-12 | 1994-05-17 | Nippon Soken, Inc. | Semiconductor power device having walls of an inverted mesa shape to improve power handling capability |
| JPH04336446A (en) * | 1991-05-13 | 1992-11-24 | Toshiba Corp | Using method for semiconductor device |
| US5484738A (en) * | 1992-06-17 | 1996-01-16 | International Business Machines Corporation | Method of forming silicon on oxide semiconductor device structure for BiCMOS integrated circuits |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH01315159A (en) | Dielectric-isolation semiconductor substrate and its manufacture | |
| JPH07263541A (en) | Dielectric separation substrate and manufacture thereof | |
| JPH0799239A (en) | Semiconductor device and manufacture thereof | |
| JPS63205926A (en) | Manufacture of dielectric isolation substrate | |
| US3974006A (en) | Method of obtaining high temperature resistant assemblies comprising isolated silicon islands bonded to a substrate | |
| JPH0613593A (en) | Semiconductor substrate | |
| JP2541884B2 (en) | Method for manufacturing dielectric isolation substrate | |
| JPS6354740A (en) | Manufacture of integrated circuit substrate | |
| JP2766417B2 (en) | Manufacturing method of bonded dielectric separation wafer | |
| JPS6152572B2 (en) | ||
| US4411060A (en) | Method of manufacturing dielectrically-isolated single-crystal semiconductor substrates | |
| JP2534673B2 (en) | Method for manufacturing dielectric isolation substrate | |
| JPH01302740A (en) | Dielectric isolation semiconductor substrate | |
| JPH056883A (en) | Manufacture of semiconductor substrate | |
| JPS61182242A (en) | Manufacture of semiconductor device | |
| JPS6362252A (en) | Manufacture of dielectric isolation substrate | |
| JPH04148525A (en) | Soi substrate and its manufacture | |
| JP3465765B2 (en) | Method for manufacturing semiconductor substrate for IGBT | |
| JPS62226640A (en) | Manufacture of semiconductor device | |
| JPH05267438A (en) | Adhesion-type dielectric separation semiconductor substrate | |
| JPS6248040A (en) | Insulator isolated substrate and manufacture thereof | |
| JPS61182241A (en) | Manufacture of dielectric isolation-type semiconductor | |
| JPH0235459B2 (en) | ||
| JP2769072B2 (en) | Method for manufacturing insulating layer separated substrate | |
| JPH08222625A (en) | Manufacture of dielectric isolation board |