JPS58175845A - Structure of isolation diffusion region in semiconductor device - Google Patents
Structure of isolation diffusion region in semiconductor deviceInfo
- Publication number
- JPS58175845A JPS58175845A JP5919482A JP5919482A JPS58175845A JP S58175845 A JPS58175845 A JP S58175845A JP 5919482 A JP5919482 A JP 5919482A JP 5919482 A JP5919482 A JP 5919482A JP S58175845 A JPS58175845 A JP S58175845A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion
- substrate
- impurity
- semiconductor substrate
- diffusion region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は半導体装置の製造に当って半導体基板内に形
成される分離拡散領域の形態に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the form of isolation diffusion regions formed in a semiconductor substrate during the manufacture of a semiconductor device.
半導体基板中に2つ以上の互いに独立した素子形成頭載
を形成する場合には従来から、隣接する本子形成**を
互いに電気的に絶縁する九めに、半導体基板とは異なる
伝導形を有する領域を半導体基板KI!Ill[K貫通
するように形成する方式が広(用いられてき友、これを
分離拡散領域と呼んでいる。半導体基板がp形の場合に
は分離拡散不純物としてリンを、半導体基板がn形の場
合には分離拡散不純物としてホウ素またはアル1ニウム
が使用されてき友。そして、電力系子用半導体基板は特
殊なものを除いてn形のものが使用されている。以下、
従来のn形半4体基板に形成されてい友分離拡am域に
ついて説明する。Conventionally, when two or more independent element formation heads are formed in a semiconductor substrate, adjacent element formations** are electrically insulated from each other. Semiconductor substrate KI area! A method of forming the Ill [K through it is widely used (this is called an isolation diffusion region).If the semiconductor substrate is a p-type, phosphorus is used as an isolation diffusion impurity; if the semiconductor substrate is an n-type, phosphorus is used as an isolation diffusion impurity. In some cases, boron or aluminum is used as a separated and diffused impurity.And, except for special cases, n-type semiconductor substrates are used for power system devices.
An explanation will be given of a mutually separated and expanded region formed on a conventional n-type half-quad substrate.
第1図(a)〜(C)は従来のp形不純物としてホウ系
のみを使用する場合の各工m段階での状態を示す断面図
で、まず、第1図(a) K示すように、半導体基板(
以下単に基板という、)[11の表面に形成され九酸化
@(2)の不純物拡散を行なうべI!額城に対応する部
分を写真製版法によって選択的に除去し、次に第1図(
t+) K示すようKその除去部分を含めて両表面全@
ticホウ卓を付1(以下デボジシ・田ンという。)5
せて拡散不純物層(1)を形成し、更に高温(1200
℃以上)で基板(1)を熱処理し、l@1図(0)に示
すように所定の分離拡散領域(4)を形成する。Figures 1 (a) to (C) are cross-sectional views showing the state at each process stage when only boron is used as the conventional p-type impurity. First, as shown in Figure 1 (a), , semiconductor substrate (
(hereinafter simply referred to as the substrate) [11] Impurity diffusion of nona oxide @ (2) is performed. The part corresponding to the frame was selectively removed by photolithography, and then the image shown in Figure 1 (
t+) All surfaces on both sides including the removed part as shown
Attached to the tic table 1 (hereinafter referred to as ``debojishi'') 5
to form a diffused impurity layer (1), and further heated to a high temperature (1200℃).
The substrate (1) is heat-treated at a temperature of 1° C. or above) to form a predetermined isolation diffusion region (4) as shown in FIG.
p形不純物としてホウ素を用いた場合は上述のように工
程が比軟的簡単であるが、ホウ素のシリコンに対する拡
散係数が小さく実用的には拡散深さが100〜120μ
m以下に止まるので、基板+11の厚さはgooμm楊
度以下にする必要があり、基板(11が工程途上で割れ
やすく、大きな基板を用いる仁とができない。When boron is used as the p-type impurity, the process is relatively simple as described above, but the diffusion coefficient of boron to silicon is small and the practical diffusion depth is 100 to 120 μm.
Since the thickness of the substrate 11 must be less than 0.0 m, the thickness of the substrate 11 must be less than 0.0 m, and the substrate 11 is easily broken during the process, making it impossible to use a large substrate.
#!2図(&)〜((1)は従来のp形不純物としてア
ルミニウムのみを5用いた場合の各工程段階での状aを
示す断面図で、まず第2図(SL) K示すようVζ、
第1図の場合と同様に、基板(1)の表向の酸化膜(2
)の所要部分を選択的に除去し、次に第2図(b)に示
すよう[12化Ii!i!除去部分を含めて両表面全面
にアルミニウムま之はアルオニウム。シリコンなどの拡
散不純物(5)をiI&樹法などによって何者8せ、さ
らに42図(o)K示すように、拡散すべき領域に対応
する部分以外の拡散不純物(6)を写真製版法によって
選択的に除去し、必要に応じて陽極酸化などの化学処理
を施し、次に基板(111c t%i温(1200’C
以上)で熱処理モーして@2図(d)に示すように所望
の分離拡散領域(6)を形成する。#! Figures 2 (&) to (1) are cross-sectional views showing the state a at each process step when only aluminum is used as the conventional p-type impurity. First, as shown in Figure 2 (SL) K, Vζ,
As in the case of FIG. 1, the oxide film (2) on the surface of the substrate (1)
) is selectively removed, and then, as shown in FIG. 2(b), [12Ii! i! The entire surface of both sides, including the removed parts, is made of aluminum and is made of alumonium. Diffusion impurity (5) such as silicon is made by II and tree method, etc., and as shown in Fig. 42(o)K, the diffusion impurity (6) other than the part corresponding to the region to be diffused is selected by photolithography. If necessary, chemical treatment such as anodic oxidation is performed, and then the substrate (111c t%i temperature (1200'C
A heat treatment is performed in the above steps to form desired separation and diffusion regions (6) as shown in Figure 2 (d).
上述のように、p形不純物としてアルにラム′を使用す
る場合は工程が複雑となりコストが媚くなるが、反面ア
ル建ニウムのシリコンに対する拡散係数はホウ素の場合
のそれに比較して約6倍相度の大赤さを有し、拡散Rざ
を200μm以上にすることが可能であり、基板【11
の厚さを厚くすることができ、従って、基板1110大
115を大きくできる。As mentioned above, when ram' is used for aluminum as a p-type impurity, the process becomes complicated and the cost becomes low, but on the other hand, the diffusion coefficient of aluminum for silicon is about 6 times that of boron. It has a high degree of redness, it is possible to make the diffusion radius 200 μm or more, and the substrate [11
The thickness of the substrate 1110 can be increased, and therefore the size of the substrate 1110 can be increased.
しかし、縦方向の拡1kK対して横方向への拡散法が9
は0・9倍根度であることが知られておシ、分離拡散R
δを深くすると、基板(11の表面の分離拡散領域(@
)で囲われる索子形成の有効面積(図では幅W、で示す
)が狭くなり、この面から所定の索子を形成する場合基
板の大きざを大きくする必要を生じる。However, the horizontal diffusion method is 9kK for the vertical expansion of 1kK.
It is known that R is 0.9 times radical, and separation and diffusion R
When δ becomes deeper, the isolation diffusion region (@
) is narrowed (indicated by width W in the figure), and when forming a predetermined cord from this surface, it becomes necessary to increase the size of the substrate.
以上のように従来の単一のp形不純物を用いた方式では
ホウ素を用い九場合も、アルミニウムを用いた場合もそ
れぞれ欠点を有している。As described above, conventional methods using a single p-type impurity have drawbacks, both when boron is used and when aluminum is used.
こめ発明は以上のような点に鑑みてなされたもので、基
板の票子形成表iii側からは拡散係数の小さい不純物
を、裏面側からは拡散係数の大きい不純物を拡散させる
ことによって、素子形成有効面積率を大きく保持しつつ
、十分厚さの厚い基板を使用できる分離拡散領域の構成
を提供することを目的としている。The present invention was made in view of the above points, and it is possible to effectively form elements by diffusing impurities with a small diffusion coefficient from the tag-forming front side of the substrate and diffusing impurities with a large diffusion coefficient from the back side. It is an object of the present invention to provide a configuration of an isolation diffusion region that allows the use of a sufficiently thick substrate while maintaining a large area ratio.
第3vA(a)〜(d)はこの発明の一実施例を説明す
る之めのその形成主要段階における状態を示す断面図で
、まず、#I3図<&)に示すように、従来と同様に、
基板(1)の両表面の酸化膜(2)の所要部分を選択的
に除去し、次IC$3図(功に示すように、酸化膜(2
)の除去部分を含めて表面全面にホウ素からなる第1O
拡畝不純物(3)をデポジットし、裏面全面にアルミニ
ウムおよびシリコンを蒸着し第2の拡散不MA1111
m t5Jを形成する。つづいて、第3図(c) K
示すように、lIt向の上記第2の拡散不純物m (5
7のうち、拡散−tべき鎖酸に対応する部分を残して他
の部分を写真製版法で除去し、その後に基板111 K
高温熱処理を施して、第八図((1) K示すように、
基板tl+の表面−にホウ卓拡敏偵域(4)、裏面側に
アルミニウム拡fL−域(6)を形成させ、所望の分離
拡散領域を構成する。最後に、不必要になつ7を第2の
拡散不純物層(5)を化学的に除去する。3vA(a) to (d) are cross-sectional views showing the state at the main stages of formation for explaining one embodiment of the present invention. First, as shown in Figure #I3<&), To,
Required portions of the oxide film (2) on both surfaces of the substrate (1) are selectively removed, and the oxide film (2) is then removed as shown in Figure 3 of the IC.
) is coated on the entire surface including the removed portion of boron.
Deposit the expanding ridge impurity (3), then evaporate aluminum and silicon on the entire back surface to form the second diffusion impurity MA1111.
Form m t5J. Next, Figure 3(c) K
As shown, the second diffusion impurity m (5
Of 7, the part corresponding to the diffusion-t chain acid is left and the other part is removed by photolithography, and then the substrate 111K is removed.
After high-temperature heat treatment, as shown in Figure 8 ((1) K,
An expanded fL area (4) is formed on the front side of the substrate tl+, and an aluminum expanded fL area (6) is formed on the back side of the substrate tl+ to form a desired separation/diffusion area. Finally, the second diffusion impurity layer (5), which is no longer needed, is chemically removed.
上記実施例において、裏面側にアルミニウムのみならず
シリコンをも蒸着するのはアルミニウムの拡散製置およ
υ拡散深さの均一化を計る九めで。In the above embodiment, not only aluminum but also silicon is vapor-deposited on the back side in order to uniformize the diffusion depth of aluminum and the diffusion depth.
拡散すべ8m域に対応する部分以外の拡散不純物層を除
去するのはアルミニウムと酸化膜(2)とが熱処理時に
反応して、酸化膜(2)がマスク機能を失うのを防ぐ友
めである0発明者らの経験では表躾分離拡赦を14##
に行なつ几場合、熱処城温度15150”C1ζおいて
140時間程度の拡散時間で表面のホウ索拡散領域(4
)の深さは100μm、裏面のアルミニウム拡散領域(
6)の1!lI!さは240μmが安定して得られる。The purpose of removing the diffused impurity layer other than the portion corresponding to the 8 m diffusion area is to prevent aluminum and the oxide film (2) from reacting during heat treatment and causing the oxide film (2) to lose its masking function. In the inventors' experience, the separation of public discipline and amnesty is 14##
In the case of a heat treatment temperature of 15,150"C1ζ, the diffusion time of about 140 hours results in the diffusion of borax on the surface (4
) is 100 μm deep, and the aluminum diffusion region (
6) No. 1! lI! A thickness of 240 μm can be stably obtained.
従って、基板[11の厚さは30′0μmのものを用い
ることができる。しかも、表面側はホウ素の拡散M数が
小ざいので素子形成有効面積(図では幅Wよで示す)を
大きくとれる。Therefore, the thickness of the substrate [11] can be 30'0 μm. Moreover, since the diffusion number M of boron is small on the surface side, the effective area for forming the element (indicated by the width W in the figure) can be increased.
なお、表裏両拡散頌域は同時に形成しても、態別に形成
してもよい。Incidentally, both the front and back diffusion regions may be formed at the same time or may be formed separately.
以上説明したように、この発明では半導体基板の素子形
成側の表面からは拡散係数の小さい第1の不純物を拡散
させて浅い第1の拡散領域を形成し、裏面からは拡散係
数の大きい#I2の不純物を拡散させて深い第2の拡散
領域を形成し、これらの第1および第2の拡散領域を連
結させて分離拡散領域が構成されているので、上記表面
側では素子形成有効面積率を太き(保持しつつ、分離拡
散領域の拡敏厚さを太き(とれるので、厚さの厚い基板
を用いることができ、基板の破損のおそれも著しく減少
する。As explained above, in the present invention, the first impurity having a small diffusion coefficient is diffused from the surface of the semiconductor substrate on the element formation side to form a shallow first diffusion region, and #I2 having a large diffusion coefficient is diffused from the back surface. The impurity is diffused to form a deep second diffusion region, and these first and second diffusion regions are connected to form a separation diffusion region. Since the diffusion thickness of the isolation diffusion region can be increased while maintaining the thickness, a thick substrate can be used, and the risk of damage to the substrate is significantly reduced.
#1lE(a)〜(0)は従来のp形不純物としてホウ
素のみを用い次場合の分離拡散領域の形成4機の主要段
階での状態を示す断面図、第2図(a)〜(d)はp形
不純惰としてアル<ニウムのみを用い北場合の分離拡散
領域の形成過橿の主要段階での状態を示す1li−図、
第3図(5L)〜(d)はこの発明の一実織例を説明−
rるためにその形成過程の主要段階での状態をボナ断面
図である。
図において、(1)は半導体基板、(4)はホウ素拡散
鎖酸(第1の拡散領域)、(6)はアルミニウム拡散#
4域(第2の拡散領域)である。
なお、図中同一符号は同一または相当部分を示す。
代理人 葛 舒 偵 −(外1名)
第1図 第”21図
’dJ ’7Wl−,。
第!3図#1lE (a) to (0) are cross-sectional views showing the main stages of four separate diffusion region formation processes using only boron as the conventional p-type impurity; Figures 2 (a) to (d) ) shows the state at the main stage of formation of a separated diffusion region in the case of using only aluminum as the p-type impurity,
Figures 3 (5L) to (d) illustrate an example of the weaving of this invention.
FIG. 3 is a cross-sectional view of the main stage of the formation process. In the figure, (1) is a semiconductor substrate, (4) is a boron diffusion chain acid (first diffusion region), and (6) is an aluminum diffusion #
4 region (second diffusion region). Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Ge Shu Di - (1 other person) Figure 1 Figure 21'dJ '7Wl-,. Figure 3
Claims (1)
ぞれ不純物を選択的に拡散3せて上記半導体基板をその
厚さ方向に貫通するように形成され第2の伝導形を有し
上記半導体基板を少なくとも2つの部分に電気的に分離
絶縁する分離拡散領域の構造において、上記半導体基板
の半導体系予形成側の表面からは拡散係数の小さい第1
の不純物を拡散させて浅い第1の拡散領域を形成し、上
記半導体基板の裏面からは拡散係数の大きい第2の不純
物を拡散させて深い#I2の拡散領域を形成し、上記a
11およびII2の拡散領域を連結させてなることを特
徴とする半導体装置における分離拡散−城の構造。 (2) 半導体基板がn形の基板であり、第1の不純
物にホウ素、第2の不純物にアルミニウムを用いたこと
を特徴とする特ifF請求の範囲第1項記載の半導体装
置における分離拡散領域の構造。[Scope of Claims] (A second semiconductor substrate formed to penetrate the semiconductor substrate in its thickness direction by selectively diffusing impurities from both the front and back principal directions of a semiconductor substrate of the conduction type 11). In the structure of the isolation diffusion region which has a conductive type and electrically isolates the semiconductor substrate into at least two parts, a first region having a small diffusion coefficient is separated from the surface of the semiconductor substrate on the side where the semiconductor system is preformed.
A shallow first diffusion region is formed by diffusing an impurity, and a second impurity having a large diffusion coefficient is diffused from the back surface of the semiconductor substrate to form a deep #I2 diffusion region.
1. A separation diffusion-castle structure in a semiconductor device, characterized in that diffusion regions No. 11 and II2 are connected. (2) The isolation diffusion region in the semiconductor device according to claim 1, wherein the semiconductor substrate is an n-type substrate, boron is used as the first impurity, and aluminum is used as the second impurity. structure.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5919482A JPS58175845A (en) | 1982-04-07 | 1982-04-07 | Structure of isolation diffusion region in semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5919482A JPS58175845A (en) | 1982-04-07 | 1982-04-07 | Structure of isolation diffusion region in semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58175845A true JPS58175845A (en) | 1983-10-15 |
Family
ID=13106360
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5919482A Pending JPS58175845A (en) | 1982-04-07 | 1982-04-07 | Structure of isolation diffusion region in semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58175845A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03250729A (en) * | 1990-02-28 | 1991-11-08 | Rohm Co Ltd | Manufacture of semiconductor element |
FR2783353A1 (en) * | 1998-09-16 | 2000-03-17 | St Microelectronics Sa | INSULATION WALL BETWEEN POWER COMPONENTS |
JP2016189411A (en) * | 2015-03-30 | 2016-11-04 | 新電元工業株式会社 | Semiconductor device manufacturing method |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53137685A (en) * | 1977-05-06 | 1978-12-01 | Nec Corp | Manufacture for semiconductor device |
-
1982
- 1982-04-07 JP JP5919482A patent/JPS58175845A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53137685A (en) * | 1977-05-06 | 1978-12-01 | Nec Corp | Manufacture for semiconductor device |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03250729A (en) * | 1990-02-28 | 1991-11-08 | Rohm Co Ltd | Manufacture of semiconductor element |
FR2783353A1 (en) * | 1998-09-16 | 2000-03-17 | St Microelectronics Sa | INSULATION WALL BETWEEN POWER COMPONENTS |
EP0987751A1 (en) * | 1998-09-16 | 2000-03-22 | STMicroelectronics S.A. | Isolation wall between power devices |
US6559515B1 (en) | 1998-09-16 | 2003-05-06 | Stmicroelectronics S.A. | Insulating wall between power components |
JP2016189411A (en) * | 2015-03-30 | 2016-11-04 | 新電元工業株式会社 | Semiconductor device manufacturing method |
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