JPS62249425A - Semiconductor device - Google Patents

Abstract

PURPOSE:To protect the end parts of a PSG film from being etched in the process after the PSG film is formed by covering a film such as the PSG film which has high etching speed with a film which has low etching speed. CONSTITUTION:In a passivation process, at first a hot oxide SiO2 film 1 and a PSG film 2 are successively formed on the surface of a semiconductor substrate 6 and a predetermined part is etched for 1st window opening W1 for an electrode. If steps are formed between the hot oxide SiO2 film 1 and the PSG film 2 as shown in the figure at that time and a CVD-SiO2 film 3 is formed to cover the surface, the PSG film 2 is perfectly covered with the CVD-SiO2 film 3 at the stepped parts. Then, if 2nd window opening W2 for an electrode is performed at the part where the end parts of the PSG film 2 are not exposed, in the process of forming a passivation film, a film which has high etching speed such as the PSG film can be protected including its end parts with a film which has low etching speed such as the CVD-SiO2 film 3.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to semiconductor devices, and particularly to passivation of PN junctions, and particularly to protection of a film with a high etching rate in a passivation film composed of a plurality of layers. The present invention relates to a membrane structure suitable for.

[Conventional technology]

Passivation of a PN junction is done by thermally applying the
Or chemically formed 5iOz, a film such as phosphorus glass (hereinafter referred to as PSG), which aims to prevent contamination with Na, etc. and stabilize the characteristics, and an oxide formed to protect the PSG film! , (hereinafter referred to as CVD-8j02) (
(See Japanese Patent Application Laid-Open No. 47-45378). Passivation 1 After forming the IiI film, the desired area is removed by photo-etching to attach the electrode, but in the past, complete passivation d
After forming.

Etching of the window opening for the electric kettle was being carried out.

[Problem that the invention seeks to solve]

The above-mentioned conventional technology is based on thermal oxidation 5iCh[1, PaCl2 and CVD
After sequentially forming the 5iCh films 3, the thermal oxide film 1 and the CVD 5i02 film 3 were formed by photo-etching the electrical window W for forming the cathode 3d (b3).
PSGS2O2, which has a faster etching speed than that of PSGS2O2, is overetched at the open end. Figure 2 shows a structure with electrodes 4.5 attached, but even in the process of attaching electrodes D, the etching of PS (42) progresses during cleaning treatment, etc., and the PSG
Since the S2O2 area expands, it becomes easier for contamination sources such as Na to infiltrate. The characteristics of the PN junction of the semiconductor substrate 6 become unstable if the Pazovanion is poor, so the characteristics can be stabilized with PSG model 2. However, as mentioned above, consideration was not given to the edges of the PSG desert, and there was a problem that the characteristics became unstable.

An object of the present invention is to provide a semiconductor device in which the edge of the PSG film is prevented from being etched in a step after forming the PSA model.

[Means for solving problems]

The above object is achieved by replacing a film with a fast etching rate with a film with a slow etching rate.

[Effect]

By dividing the formation of the passivation film into two steps.

Since the PSG film could be sealed with CVD 810z, the passivation film seen from the outside looked like CVD5 i.
Only Ch. Therefore, in the subsequent process, side etching of the PSG film by the chemical α immersion is prevented, and the properties of the PSG film can be kept stable.

〔Example〕

1 One embodiment of the present invention will be explained with reference to FIG. In FIG. 1, the surface of the semiconductor substrate 60PN junction is protected by a thermally oxidized 5iOz film 1 and a passivation film made of CVD 5iOz3 that blocks PSGS2O2PSGg2, and electrodes 4 and 5 are provided in the portion where the passivation film is removed. . Figure 4 shows an example of the formation of a passivation film. Figure 4(a)
Thermal oxidation 8102 film 1 and PS
GS2O secondary formation. Next, as shown in FIG. 4(b), a predetermined position is etched to perform the first electrode window opening W+f:. At this time, a black step as shown in the figure is created between the thermally oxidized 8102 film 1 and the PEG film 2. That is, thermal oxidation S t 02 model is PSGS2O2 wide <, PSGIII
When looking at the semiconductor substrate 6 from the 2 side, the thermally oxidized 5iCh film can also be seen. Furthermore, as shown in FIG. 4(C), CVD 8i02
3 is deposited and formed. Then, thermally oxidized 5IO2 film 2 and PSG
In the S2O2 difference part, the PEG film 2iCvD-8iCh3 is definitely 1. After the first stage, the second electrode window opening W2 is carried out in a place where the PSGS2O2 part is not exposed, as shown in Fig. 4(d). By this, the structure of the present invention can be obtained. As described above, the present invention can be implemented through simple steps and can be applied to planar junction structures such as transistors, thyristors, and GTO thyristors.

Applicable to all mesa junction structures.

〔Effect of the invention〕

According to the present invention, a film with a high etching rate such as a PSG film can be protected up to its edges with a film with a different etching speed such as CVDSiO2 by passivation beak film formation, so that the contamination prevention function of the PSG film can be improved. This has the effect of providing a semiconductor device with a highly reliable passivation film that can make maximum use of the passivation film.

[Brief explanation of drawings]

FIG. 1 is a partial vertical cross-sectional view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a partial vertical cross-sectional view of a conventional semiconductor device, and FIG.
The figure shows an example of forming a passivation film in a conventional semiconductor device D, and FIG. 4 shows an example of forming a passivation pattern in a semiconductor device of the present invention.

Claims (1)

[Claims] 1. A semiconductor substrate has at least one PN junction, a PN junction end is exposed on at least one main surface of the semiconductor substrate, and a passivation film is provided at the PN junction end. In the semiconductor device in which the passivation film is formed, the passivation film is composed of at least two layers, and the first film among the passivation constituent films has a slow etching rate, and the second film, which has a fast etching rate, is not exposed. so the second
A semiconductor device characterized by covering a film of. 2. In claim 1 above, a third film with a slow etching rate is interposed between the second film and the semiconductor substrate, the third film is wider than the second film, and the second film is wider than the second film. A semiconductor device characterized in that a third film is visible when the semiconductor substrate is viewed from the film side.