JPS6399575A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To form both gate electrodes on the same semiconductor substrate, by forming the gate electrode of an MIS element on the surface of the semiconductor substrate, and thereafter forming the gate electrode of an MIS element constituting a nonvolatile memory on the surface of the semiconductor substrate. CONSTITUTION:As an interlayer insulating film 12, e.g., a CVD film is formed. A contact hole 13 is provided in an ordinary Si gate step. An oxide film 15 is formed on the contact hole by thermal oxidation or CVD. An Si substrate is exposed only at a region 16 including the channel region of an MNOS element by photoetching. A very thin oxide film 20 (20-100Angstrom ) is formed at a region which is to become the gate of the MNOS element. A nitride film 21 is formed on the entire surface thereon. The nitride film and the oxide film at the contact part are removed by photoetching. Then Al is evaporated, and patterning is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for manufacturing a semiconductor integrated circuit device in which a circuit including a nonvolatile memory and a circuit constituting a microconverter are provided on the same substrate.

Currently, MN OS is a rewritable non-volatile memory.
(Metal-Ni tride-Oxide-8e
Microconductor type devices are used. This memory stores stored information by applying high voltages of 10 and - to the gate electrode to accumulate and release charges at the boundary between the nitride film and the oxide film through a thin oxide film. It is. The main MIS elements that make up this memory usually have gate electrodes,
The nitride film as a gate insulating film has a thickness of about 500A, and the thin oxide film has a thickness of about 2OA.The process is similar to a normal Al gate type MOS process.

On the other hand, the development of control semiconductor devices has been remarkable, and micropn viewers are currently using one-chip or several-chip LS.
I is being manufactured. These LSIs have become extremely highly integrated and have improved performance. For this reason, a Si gate process is usually used as a manufacturing process.

Furthermore, considering future performance improvements, it is thought that a high-performance Si gate process will become available.

On the other hand, when considering the application aspect of microcomputers, nonvolatile memories are becoming necessary as peripheral ICs. Currently, microcomputers and nonvolatile memory are manufactured as separate LSIs and ICs, and used in combination.
However, considering future performance improvements, it is desirable to form them on the same chip in terms of integration degree, cost, performance, etc. However, as mentioned above, each process is completely different, and so far this has not been realized.

As a method for realizing this, it is considered that the circuit element and the nonvolatile memory element can be relatively easily formed on the same chip by using the A gate process, which is similar to that used to make the MNO8 element. However, in this method, since the circuit element is formed with an Al gate structure,
Compared to the Si gate process used in current microcomputers, the integration and speed will be worse, making it impossible for current microcomputers to compete.

On the other hand, when considering the simultaneous fabrication of 8 non-volatile memory MNO elements using the Si gate process used to make microcomputers, heat treatment of the Si gate process may deteriorate the retention characteristics of the non-volatile memory elements, or the process may be delayed. It has drawbacks such as being extremely complex and has not yet been realized.

For the above reasons, nonvolatile memories and microcomputers are currently manufactured separately.

The present invention provides a method for manufacturing a semiconductor integrated circuit device that can be easily formed on the same chip and can be realized without sacrificing the drawbacks of both.

According to the present invention, it is possible to easily form a non-volatile memory (non-volatile memory) on a highly integrated, high-speed, high-performance chip formed by a Si gate process without compromising performance.
As a result, separate chips had to form the system. The system can be formed with one chip. On the other hand, by incorporating non-volatile memory into a microcomputer, it is unlikely that the process of the microcomputer chip will become complicated or the price will increase.

The present invention will be described below with reference to embodiments shown in the accompanying drawings.

An example in which an N-channel MNOS is formed in a %C-MO8Si gate process will be shown below, but the same will apply to Mo or W gates instead of Sl gates in order to improve performance in the future. Also, as for MNOS, the same is of course true for P-channel.

Figure 1 shows MN of AA' gate in C-MO8Si gate.
An example in which an OS is formed on the same substrate is shown. The S1 gate process forms a p-channel device. This is exactly the same as a normal Sl gate. On the other hand, non-volatile notes! JMNO8 uses the l wiring in the Si gate structure as a gate electrode.

Therefore, an extra gate electrode layer for forming the MNO8 structure is unnecessary. Furthermore, the nitride film used in the MNO8 structure can extend to the top of the interlayer CVD film on circuit elements formed with other Si gate structures, thereby improving passivation properties. realized at the same time.

From the above, the high speed achieved by the Si gate structure.

A highly integrated, high-performance circuit element, an MNO8 element with good characteristics due to the Al gate structure, and good passivation characteristics due to the nitride film can be obtained.

Next, an example of the manufacturing method of the present invention will be shown.

FIG. 2 is a part of a SiG CMOS process, and shows a state in which impurities are selectively doped by diffusion or implantation using a mask 10. Here, by using a mask 10 for selectively doping impurities, the source and drain of the MNO8 element are doped with impurities and the region that will become the channel region is separated.

Next, a CVD film, for example, is formed as the interlayer insulating film 12, and a contact hole 13 is formed in a normal Si gate process. At this time, contact holes to the sources and drains of the MNO8 elements and the MNO
Drill a hole in the gate area [14] of the 8 elements (Figure 3).

Next, an oxide film 15 is formed on the contact hole by thermal oxidation or CVD, and an M
Only the Si substrate 16 including the channel region of the NO8 element is exposed. By leaving the oxide film 15 formed at this time in the channel region (and going through the steps described below), an insulated gate transistor equivalent to a device made by a normal M-gate process can be formed. It is actually used as the switch MO8 required in the MNO8 type nonvolatile memory (this figure is not particularly shown in this example).Therefore, approximately 500A is appropriate for the oxide film 15 (Fig. 4). .

Next, there is a very thin (
20-100A) An oxide film 20 is formed, and a nitride film 21 is formed on the entire surface thereof. At this time, in order to improve the characteristics of the MNO8 element, a step such as forming an impurity layer at the interface between the thin oxide film and the nitride film may be included.

Further, in order to form a contact hole 22, the nitride film and oxide film at the contact portion are removed by photo-etching (FIG. 5).

Next, by depositing Kl and performing patterning, a structure as shown in FIG. 1 is completed.

Although one example of the manufacturing method has been shown above, it can be realized by various other methods. for example.

The contact hole and the MNOS gate region may be formed in separate photoetching steps. That is, a method may be employed in which the contact portion is formed after first photoetching the gate region, forming a thin oxide film, and forming a nitride film.

Alternatively, in order to form the channel region of the MNOS, a method may be used in which the thick oxide film in the field portion is directly photo-etched without using a selective doping mask for impurity doping.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a semiconductor integrated circuit device formed by the manufacturing method of the present invention, and FIGS. 2 to 5 are cross-sectional views showing the manufacturing method of the semiconductor integrated circuit device according to the present invention in order of steps. DESCRIPTION OF SYMBOLS 1... Oxide film, 2... Gate oxide film, 3... Polycrystalline silicon film for gate electrodes, 4... Interlayer insulating film, 5...
... Nitride film, 6... Thin oxide film, 7... Aluminum wiring (electrode), 10... Mask film, 11.
... N+ type layer, 12... PSG film, 21... Nitride film. Figure 1

Claims (1)

[Claims] 1. A method for manufacturing a semiconductor integrated circuit device in which a first circuit including an MIS element constituting a nonvolatile memory and a second circuit including an MIS element other than the MIS element are formed on the same semiconductor substrate. There is an MIS in the second circuit on the surface of the semiconductor substrate.
A method for manufacturing a semiconductor integrated circuit device, characterized in that after forming a gate electrode of an element, a gate electrode of a MIS element constituting a nonvolatile memory of the first circuit is formed on a surface of the semiconductor substrate. 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein a complementary MIS element including a P channel and an N channel is formed as the MIS element in the second circuit.