JPS62115778A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To form a nonvolatile memory easily on a semiconductor chip formed by an Si gate process, by forming on the same chip a nonvolatile memory member constructed of an MIS element and a C-MOS member constructed of another MIS element. CONSTITUTION:Impurity doping of the source and drain of an MNOS element and isolation of a channel region are conducted by using a mask 10. An interlayer insulation film 12 is formed, and a contact hole 13, contact holes for the source and drain of the MNOS element and a hole for a part to be a gate region 14 of the MNOS element are opened. An oxide film 15 is formed on the contact hole, and an Si substrate is exposed only in a region 16 containing the channel region of the MNOS element, a very thin oxide film 20 is formed in the region which is to serve as the gate of the MNOS element, a nitride layer 21 is formed on the whole surface thereof. The nitride film and the oxide film in the contact portions are removed. Next, Al is evaporated, and patterning is conducted.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, etc. in which a circuit including a non-volatile memory and a circuit constituting a microcomputer are provided on the same substrate. Through optimization, a semiconductor integrated circuit device that is more optimal as a whole is provided.

Currently, MN OS is a rewritable non-volatile memory.
(Met a l -Nit r i de -
Ox ide-8 conductor) type is used. This memory stores information by applying high voltages of 10 and - to the gate electrode to accumulate and release charges at the boundary between the nitride film and the oxide film through the thin oxide film. It is something. The main MIS elements constituting this memory usually use AA as the tartite electrode, the nitride film as the gate insulating film has a current of about 500A, and the thin oxide film has a current of about 200A.
Approximately 0 A is used, and the process is similar to a normal M-gate type MOS process.

On the other hand, the development of control semiconductor devices has been remarkable, and microcomputers are currently using one or several chips of LS.
I is being manufactured. These LSIs have become extremely highly integrated and have improved performance. For this reason, a Si gate process is usually used as a manufacturing process.

Furthermore, considering future performance improvements, it is thought that a high-performance Si gate process will be adopted.

On the other hand, when considering the application of microcombinators, nonvolatile memory is becoming necessary as one peripheral IC.

Currently, the microcomputer and non-volatile memory are separate LS1. Although they are manufactured as ICs and used in combination, in consideration of future performance improvements, it is desirable to form them on the same chip in terms of degree of integration, cost, performance, etc. However, as mentioned above, each process is completely different and has not been realized at present.

As a method to realize this, A! It is conceivable that a circuit element and a nonvolatile memory element can be relatively easily formed on the same chip by using the getter process. However, in this method, since the circuit element is formed with an AA getter structure,
Compared to the Si gate process used in current microcomputers, it will be inferior in terms of integration and speed, and will not be able to compete with current microcomputers.

On the other hand, considering that non-volatile memories MNO8 are simultaneously manufactured using the Si gate process used to manufacture microcomputers, the heat treatment of the Si gate process
This method has disadvantages such as deterioration of the retention characteristics of nonvolatile memory elements and extremely complicated processes, so it has not yet been realized.

For the reasons mentioned above, non-volatile memory microcomputers are currently manufactured separately.

An object of the present invention is to provide a semiconductor integrated circuit device that can be easily formed on the same chip and can be realized without sacrificing the drawbacks of both.

The present invention will be described below with reference to embodiments shown in the accompanying drawings.

An example in which an N-channel MNOS is formed in a C-MOS Si gate process will be described below, but it does not need to be a C-MOS, and may be an N-channel or a P-channel.

Further, in order to improve performance in the future, the same applies to M0 gates or W gates instead of Si gates. Also, as for MNOS, the same is of course true for P-channel.

Figure 1 shows an MNO with an Ak getter on a C-MOSSi gate.
An example is shown in which S is formed on the same substrate. N-channel and P-channel devices are formed by the Si gate process. This is exactly the same as a normal Si gate. On the other hand, non-volatile notes! JMNO8 uses the Ap wiring in the Si gate structure with the gate as a pole.

Therefore, an extra gate electrode layer for forming the MNO8 structure is unnecessary. Furthermore, the nitride film used in the MNO8 structure can extend to the top of the interlayer CVD film on circuit elements formed with other Si gate structures, which improves the passivation properties. are realized at the same time.

From the above, the high speed achieved by the Si gate structure.

A highly integrated, high-performance circuit element, an MNO8 element with good characteristics due to the Ak getter structure, and good passivation characteristics due to the nitride film can be obtained.

Next, an example of a manufacturing method will be shown.

FIG. 2 shows a part of a Si gate CMOS process, and shows a state in which impurities are selectively doped by diffusion or implantation using a mask 10. Here, by using a mask 10 for selectively doping impurities, the source and drain of the MNO8 element are doped with impurities and the region to be the channel region is separated.

Next, a CVD film, for example, is formed as the interlayer insulating film 12, and contact holes 13 are formed in a normal Si gate process. At this time, contact holes to the source and drain of the MNO8 element and the MN
A hole is made in the portion that will become the gate region 14 of the O8 element (FIG. 3).

Next, an oxide film 15 is formed on the contact hole by thermal oxidation or CVD, and an M
Only the region 16 including the channel region of the NO8 element is exposed on the Si substrate. If the oxide film 15 formed at this time is left in the channel region, the process described below can be performed.
It is possible to form an isolated gate type transistor equivalent to a device made by a more usual AA getter process. Further, this element is actually used as a switch MOS required in the MNO8 type nonvolatile memory (this figure is not particularly shown in this example). Therefore, the appropriate thickness for the oxide film 15 is about 500A (FIG. 4).

Next, there is a very thin (
20-100A) An oxide film 20 is formed, and a nitride film 21 is formed on the entire surface thereof.

At this time, in order to improve the characteristics of the MNO8 element, a step such as forming an impurity layer at the interface between the thin oxide film and the nitride film may be included.

Further, in order to form a contact hole 22, the nitride film and oxide film at the contact portion are removed by photo-etching (FIG. 5).

Next, A2 is deposited and patterned.
The structure shown in the figure is completed.

Although one example of the manufacturing method has been shown above, it can be realized by various other methods. For example, the contact hole and the MNOS gate region may be formed in separate photo-lithography processes. That is, a method may be employed in which the contact portion is formed after first photoetching the gate region, forming a thin oxide film, and forming a nitride film.

Also, K to form the channel region of MNOS.

Alternatively, the thick oxide film in the field portion may be directly photo-etched without using a selective doping mask for impurity doping.

In any case, in the device according to the embodiment of the present invention described above, after forming a circuit element pattern using a Si gate process, a thin oxide film and a nitride film are formed in the MNOS part, and wiring electrodes are formed in the MNO8 element. The purpose is to use it as a gate electrode.

According to the present invention, a nonvolatile memory can be easily formed on a high-integration, high-speed, high-performance chip formed by a Si gate process without degrading performance, and as a result, Instead of having to form the system with separate chips, the system can now be formed on one chip. On the other hand, adding non-volatile memory to a microcomputer hardly makes the process of the microcomputer chip more complicated or increases its price.

[Brief explanation of drawings]

1 to 5 are cross-sectional views showing the insulated gate semiconductor device and the manufacturing method thereof according to the present invention in the order of steps. DESCRIPTION OF SYMBOLS 1... Oxide film, 2... Gate oxide film, 3... Polycrystalline silicon film for gate electrodes, 4... Interlayer insulating film, 5...
... Nitride film, 6... Thin oxide film, 7... Aluminum wiring (electrode →, 10... Mask film, 11...
... N+ type layer, 12... PSG film, 21... Nitride film. Agent: Patent attorney Katsuo Ogawa.

Claims (1)

[Claims] 1. A semiconductor integrated circuit in which a non-volatile memory section consisting of a first MIS element and a C-MOS section consisting of a second MIS element excluding the first MIS element are formed on the same semiconductor chip. circuit device.