JPH11354783A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the integration of SAC(self align contact) and to secure the withstand voltage of a high withstand voltage element. SOLUTION: Side wall films 24a, 24b, 25a, and 25b are arranged on the side walls of gate electrodes 23a and 23b, and a gap insulation film is arranged at the upper portion. The side wall films 24a and 24b and a cap insulation film are provided with an etching selection ratio for an interlayer insulation film, and the side wall films 25a and 25b are provided with essentially the same etching ratio as the interlayer insulation film. No side wall film 25a exists and a side wall film 24a exists between the gate electrode 23a and a contact hole 29a in a normal transistor. The side wall films 24a and 25a exist between the gate electrode 23b and the contact hole 29b in a high withstand voltage transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a MISFET in which a sidewall is disposed on a side wall of a gate electrode, and more particularly to a semiconductor device requiring two or more kinds of operating voltages, for example, an operation of a memory cell. Is
A high voltage is required, and some of the peripheral circuits are used for a flash EEPROM operating at a normal low voltage.

[0002]

2. Description of the Related Art FIG. 14 shows a conventional MISFET. A gate insulating film 12 is formed on a semiconductor substrate 11, and a gate electrode 13 is formed on the gate insulating film 12. On the side wall of the gate electrode 13, a side wall insulating film 14 called a side wall is formed. In the semiconductor substrate 11 directly below the sidewall insulating film 14, an LDD (Light
A diffusion layer 15a having a low impurity concentration called "y Doped Drain" is formed.

Further, adjacent to the diffusion layer 15a, the diffusion layer 1
Diffusion layer 15b having an impurity concentration higher than 5a is formed. On the semiconductor substrate 11, an interlayer insulating film 16 that completely covers the MISFET is formed. A contact hole 17 reaching the diffusion layer 15b is formed in the interlayer insulating film 16.
Are formed.

A contact plug 18 made of, for example, tungsten (W) is formed in the contact hole 17. The metal wiring 1 is provided on the contact plug 18.
9 are formed.

In the LSI having the MISFET having the above configuration, the alignment margin (interval) A between the gate electrode 13 and the contact hole 17 is one of the restrictions in improving the integration degree of the LSI. Therefore, a self-aligned contact (SAC) technique has been proposed that can reduce the restriction on the alignment margin between the gate electrode 13 and the contact hole 17 when improving the integration degree of the LSI.

FIG. 15 shows a conventional MISFET to which the self-aligned contact technology is applied. A gate insulating film 12 is formed on a semiconductor substrate 11, and a gate electrode 13 is formed on the gate insulating film 12. On the gate electrode 13, a cap insulating film 20 functioning as a mask when forming the contact hole 17 is formed. On the side walls of the gate electrode 13 and the cap insulating film 20, a side wall insulating film 14 called a side wall is formed. This side wall insulating film 14 is also formed in contact hole 1
7 functions as a mask at the time of formation.

In addition, the semiconductor substrate 1 immediately below the side wall insulating film 14
In FIG. 1, a diffusion layer 15a having a low impurity concentration called LDD is formed. A diffusion layer 15b having a higher impurity concentration than diffusion layer 15a is formed adjacent to diffusion layer 15a. On the semiconductor substrate 11, MI
An interlayer insulating film 16 that completely covers the SFET is formed. In the interlayer insulating film 16, a contact hole 17 reaching the diffusion layer 15b is formed.

A contact plug 18 made of, for example, tungsten (W) is formed in the contact hole 17. The metal wiring 1 is provided on the contact plug 18.
9 are formed.

The characteristics of the MISFET having the above configuration are as follows.
First, the sidewall insulating film 14 and the cap insulating film 20 function as a mask when the contact hole 17 is formed. That is, the side wall insulating film 14 and the cap insulating film 2
0 is made of a material having an etching selectivity with respect to the interlayer insulating film 16. For example, when the interlayer insulating film 16 is formed of a silicon oxide film (BPSG film or the like), the sidewall insulating film 14 and the cap insulating film 20 are formed of a silicon nitride film.

Second, even if the gate electrode 13 and the contact hole 17 overlap with each other, the gate electrode 13 and the contact plug 18 in the contact hole 17 cannot be formed because the sidewall insulating film 14 and the cap insulating film 20 exist. The point is that insulation is maintained. That is, the MISFET of this example
In this case, since the alignment margin between the gate electrode 13 and the contact hole 17 can be reduced, it is possible to contribute to the improvement of the integration degree of the LSI.

[0011]

In an LSI having a MISFET using the self-aligned contact technique as shown in FIG. The thickness is set to a minimum thickness for maintaining the insulation between the gate electrode 13 and the contact plug 18 in the contact hole 17. Thereby, as shown in FIG. 16, the contact hole 17 can be sufficiently brought close to the gate electrode 13, and the contact area Sa between the diffusion layer 15b and the contact plug 18 can be sufficiently ensured.

However, as shown in FIG. 17, when the side wall insulating film (side wall) 14 becomes thicker than necessary, when the contact hole 17 is sufficiently close to the gate electrode 13, the diffusion layer 15b and the contact plug 18 Contact area Sb becomes very small, causing a problem of an increase in contact resistance.

Also, as shown in FIG. 18, two MISs which are close to each other and share one of the two diffusion layers
In the case of an FET, when the distance between the gate electrodes 13 of the two MISFETs becomes smaller, the contact area Sc between the diffusion layer 15b and the contact plug 18 also becomes smaller. Here, as shown in FIG. 19, when the side wall insulating films (sidewalls) 14 of the gate electrodes 13 adjacent to each other come into contact, the contact holes 17 cannot reach the surface of the semiconductor substrate 11.

By the way, the gate electrode 13 of the MISFET
The side wall disposed on the side wall of (2) has a role of forming diffusion layers 15a and 15b having an LDD structure in addition to a role of realizing a self-aligned contact. The diffusion layers 15a and 15b having the LDD structure contribute to improvement of the junction breakdown voltage of the MISFET, relaxation of the hot carrier effect, relaxation of the short channel effect, and the like.

Here, in a semiconductor device using a low voltage and a high voltage inside the LSI, the side wall of the gate electrode of the MISFET operating at a low voltage is made as thin as possible (short LDD) and the contact hole is made as small as possible. There is a demand to improve the degree of integration of the LSI by approaching the gate electrode. On the other hand, there is also a demand that the sidewall of the gate electrode of a MISFET operating at a high voltage be made thick enough to ensure a withstand voltage, and that a long LDD length that can obtain a sufficient withstand voltage even at a high voltage be provided.

In other words, in order to simultaneously satisfy these two requirements, two structures having different LDD lengths in one chip are required.
It is necessary to form an ISFET. However, conventionally, such a two-structure MISF having different LDD lengths is used.
When the ET is formed in one chip, it is necessary to add a new mask forming step for that purpose, which has been difficult to realize.

SUMMARY OF THE INVENTION The present invention has been made to solve the above circumstances, and it is an object of the present invention to provide a self-aligned contact technology and a short LDD for a MISFET operating at a low voltage.
As a result, the integration degree of the LSI can be improved without increasing the contact resistance, and at the same time, for a MISFET operating at a high voltage, a long LDD and a sufficient alignment margin between the gate electrode and the contact hole can be secured. Is to obtain a high withstand voltage.

[0018]

In order to achieve the above object, a semiconductor device of the present invention comprises a MISFET formed on a semiconductor substrate and a contact hole formed on the MISFET and reaching a diffusion layer of the MISFET. A first sidewall film adjacent to the gate electrode and having a substantially lower etching rate than the interlayer insulating film when the contact hole is opened, on a sidewall of the gate electrode of the MISFET. And a second side wall film adjacent to the first side wall film and having an etching rate substantially higher than that of the first side wall film is disposed, and the second side wall film is removed at an opening of the contact hole. I have.

The MISFET has a first diffusion layer and a second diffusion layer having a higher impurity concentration than the first diffusion layer, and the first diffusion layer is provided immediately below the first side wall film. It is arranged.

On the gate electrode, a cap insulating film having substantially the same etching rate as the first side wall film is disposed. The second sidewall film has substantially the same etching rate as the interlayer insulating film. The first sidewall film remains in the opening of the contact hole.

A semiconductor device according to the present invention comprises a memory cell having a stacked gate electrode formed on a semiconductor substrate, an interlayer insulating film formed on the memory cell and having a contact hole reaching a diffusion layer of the memory cell. A first side wall film adjacent to the stacked gate electrode on the side wall of the stacked gate electrode of the memory cell and having a substantially lower etching rate than the interlayer insulating film at the time of opening the contact hole; A second sidewall film, which is adjacent to the first sidewall film and has a substantially higher etching rate than the first sidewall film, is disposed, and the second sidewall film is removed at an opening of the contact hole.

A cap insulating film having substantially the same etching rate as the first side wall film is disposed on the stacked gate electrode. The second sidewall film has substantially the same etching rate as the interlayer insulating film. The first sidewall film remains in the opening of the contact hole.

According to the semiconductor device of the present invention, the first MISFET
And a second MISFET operating at a higher operating voltage than the first MISFET.
Each of the SFETs has a first diffusion layer and a second diffusion layer having a higher impurity concentration than the first diffusion layer. Side walls of the gate electrodes of the first and second MISFETs are respectively connected to the gate electrode. A first side wall film adjacent to the first side wall film and a second side wall film adjacent to the first side wall film are arranged;
The first diffusion layer in the MISFET is disposed directly below the first sidewall film, and the first diffusion layer in the second MISFET is disposed directly below the first and second sidewall films. ing.

An interlayer insulating film having a first contact hole reaching the second diffusion layer of the first MISFET and a second contact hole reaching the second diffusion layer of the second MISFET is formed on the first and second MISFETs. The distance from the gate electrode of the second MISFET to the second contact hole is longer than the distance from the gate electrode of the first MISFET to the first contact hole.

The first sidewall film has a substantially lower etching rate than the interlayer insulating film when the first and second contact holes are opened, and the second sidewall film is etched more than the first sidewall film. Speed is substantially faster.

On the gate electrodes of the first and second MISFETs, a cap insulating film having substantially the same etching rate as the first side wall film is disposed.
The second sidewall film has substantially the same etching rate as the interlayer insulating film.

The first side wall film exists between the gate electrode of the first MISFET and the first contact hole, and the second side wall film does not exist.
Between the gate electrode and the second contact hole.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device according to the present invention will be described in detail with reference to the drawings. FIG. 1 shows a semiconductor device having a MISFET to which a self-aligned contact technique according to a first embodiment of the present invention is applied.

This semiconductor device includes a normal MISFET (normal transistor) operating at a low voltage (eg, power supply voltage) and a high voltage MISFET (high voltage transistor) operating at a high voltage (eg, boosted voltage). Have.

First, the structure of a normal transistor will be described. A gate insulating film 22a is formed on the semiconductor substrate 21, and a gate electrode 23a is formed on the gate insulating film 22a.
Are formed. On the gate electrode 23a, a cap insulating film 32a functioning as a mask when forming the contact hole 29a is formed. Sidewalls are formed on the side walls of the gate electrode 23a and the cap insulating film 32a.

The sidewall has two types of sidewall films 24a and 25a made of different materials. The sidewall film 24a is disposed adjacent to the gate electrode 23a and the cap insulating film 32a, and is made of a material having an etching selectivity with respect to the interlayer insulating film 28. That is, the sidewall film 24a is made of a material that is hardly etched when the contact hole 29a is formed, for example, a silicon nitride film when the interlayer insulating film 28 is made of a silicon oxide film.

The side wall film 25a is disposed adjacent to the side wall film 24a, and is made of a material having substantially the same etching rate as the interlayer insulating film 28. That is, the side wall film 25
a is made of a material that is etched together with the interlayer insulating film 28 when the contact hole 29a is formed, for example, the same material as the interlayer insulating film 28 (for example, a silicon oxide film).

The side wall film 25a may be made of either a conductor or an insulator.
Is preferably made of an insulator. Gate electrode 23a
This is to ensure the insulation between the contact plug 30a and the contact plug 30a. In the portion where the contact hole 29a is formed, the sidewall film 25a does not exist, but at least the sidewall film 24a exists. That is, the insulation between the gate electrode 23a and the contact plug 30a is ensured by the side wall film 24a.

In the semiconductor substrate 11 immediately below the side wall film 24a, a diffusion layer 2 called LDD having a low impurity concentration is formed.
6a are formed. That is, the L of the normal transistor
The DD length is substantially equal to the thickness of the sidewall film 24a. A diffusion layer 27a having a higher impurity concentration than the diffusion layer 26a is formed adjacent to the diffusion layer 26a. On the semiconductor substrate 11, an interlayer insulating film 28 completely covering the MISFET
Are formed.

In the interlayer insulating film 28, a contact hole 29a reaching the diffusion layer 27a is formed. The contact hole 29a may or may not overlap with the side wall film 24a. Similarly, the contact hole 29a may or may not overlap with the gate electrode 23a. The sidewall film 25a does not exist in the contact hole 29a.

In the contact hole 17, a contact plug 30a made of, for example, tungsten (W) is formed. A metal wiring 31a is formed on the contact plug 30a.

Next, the structure of the high breakdown voltage transistor will be described. A gate insulating film 22b is formed on the semiconductor substrate 21, and a gate electrode 23 is formed on the gate insulating film 22b.
b is formed. A cap insulating film 32b is formed on the gate electrode 23b. Side walls are formed on the side walls of the gate electrode 23b and the cap insulating film 32b.

The sidewall has two types of sidewall films 24b and 25b made of different materials. The sidewall film 24b is disposed adjacent to the gate electrode 23b and the cap insulating film 32b, and is made of a material having an etching selectivity with respect to the interlayer insulating film 28. When the interlayer insulating film 28 is made of a silicon oxide film, the sidewall film 24b is made of, for example, a silicon nitride film.
The side wall film 25b is disposed adjacent to the side wall film 24b, and is made of a material having substantially the same etching rate as the interlayer insulating film 28. The sidewall film 25b is made of, for example, the same material (for example, a silicon oxide film) as the interlayer insulating film 28.

In the high-breakdown-voltage transistor, a sufficient margin is provided between the gate electrode 23b and the contact hole 29b so that the contact hole 29b does not overlap with any of the gate electrode 23b and the sidewall films 24b and 25b. ing. That is, the self-aligned contact technology is not applied to the high breakdown voltage transistor.

Semiconductor substrate 1 immediately below sidewall films 24b and 25b
In FIG. 1, a diffusion layer 26b having a low impurity concentration called an LDD is formed. That is, the LDD length of the high breakdown voltage transistor is longer than the LDD length of the normal transistor by the thickness of the sidewall film 25b. Also,
A diffusion layer 27b having a higher impurity concentration than the diffusion layer 26b is formed adjacent to the diffusion layer 26b.

On the semiconductor substrate 11, an interlayer insulating film 28 that completely covers the MISFET is formed. A contact hole 29 reaching the diffusion layer 27b is formed in the interlayer insulating film 28.
b is formed. The contact hole 29b is formed so as not to overlap the side wall films 24b and 25b.

In the contact hole 29b, for example,
A contact plug 30b made of tungsten (W) is formed. A metal wiring 31b is formed on the contact plug 30b.

According to the semiconductor device having the above configuration, M
Sidewalls made of two different materials are formed on the side walls of the gate electrode of the ISFET. That is, the side wall films 24a and 24b having an etching selectivity with respect to the interlayer insulating film 28 and the side wall film 2 having substantially the same etching rate as the interlayer insulating film 28 are formed.
5a and 25b.

In a normal transistor operating at a low voltage, a side wall film 24a exists between the gate electrode 23a and the contact hole 29a.
Does not exist. Naturally, both side wall films 24a and 25a exist around the gate electrode 23a except between the gate electrode 23a and the contact hole 29a. Further, the diffusion layer 26 functioning as an LDD is provided only directly below the sidewall film 24a.
a is formed.

Therefore, the self-aligned contact and the short LDD can be used without increasing the contact resistance.
The degree of integration of the LSI can be improved. In a high breakdown voltage transistor operating at a high voltage, the contact hole 29b does not overlap with any of the side wall films 24b and 25b. Also, the side wall films 24b, 2
A diffusion layer 26b functioning as an LDD is formed immediately below 5b.

Therefore, with the long LDD, the breakdown voltage of the diffusion layer (drain) of the high breakdown voltage transistor can be ensured. As described above, in the case where the MISFET whose integration degree is to be improved by the self-aligned contact technique and the MISFET whose drain withstand voltage of the drain diffusion layer is to be sufficiently ensured are formed on the same substrate, the improvement of the integration degree of the LSI and An improvement in drain withstand voltage can be achieved at the same time.

FIG. 2 shows a MISFET to which a self-aligned contact technique according to a second embodiment of the present invention is applied.
Is shown. FIG.
It is sectional drawing which follows the I-III line.

This semiconductor device has a memory cell portion composed of memory cells having a two-layered (stacked) gate structure, and a normal M which operates at a low voltage (for example, a power supply voltage).
Peripheral circuit part consisting of ISFET (normal transistor)
And a peripheral circuit section including a high-breakdown-voltage MISFET (high-breakdown-voltage transistor) that operates at a high voltage (for example, a boosted voltage).

First, the configuration of the normal transistor in the peripheral circuit section will be described. A gate insulating film 22a is formed on a P-type semiconductor substrate (may be a well region) 21, and a gate electrode 23a is formed on the gate insulating film 22a. On the gate electrode 23a, a cap insulating film 32a functioning as a mask when forming the contact hole 29a is formed. Sidewalls are formed on the side walls of the gate electrode 23a and the cap insulating film 32a.

The sidewall has two types of sidewall films 24a and 25a made of different materials. The sidewall film 24a is disposed adjacent to the gate electrode 23a and the cap insulating film 32a, and is made of a material having an etching selectivity with respect to the interlayer insulating film 28. That is, the sidewall film 24a is made of a material that is hardly etched when the contact hole 29a is formed, for example, a silicon nitride film when the interlayer insulating film 28 is made of a silicon oxide film.

The side wall film 25a is disposed adjacent to the side wall film 24a, and is made of a material having substantially the same etching rate as the interlayer insulating film 28. That is, the side wall film 25
a is made of a material that is etched together with the interlayer insulating film 28 when the contact hole 29a is formed, for example, the same material as the interlayer insulating film 28 (for example, a silicon oxide film).

The side wall film 25a may be made of any one of a conductor and an insulator.
Is preferably made of an insulator. Gate electrode 23a
This is to ensure the insulation between the contact plug 30a and the contact plug 30a. In the portion where the contact hole 29a is formed, the sidewall film 25a does not exist, but at least the sidewall film 24a exists. That is, the insulation between the gate electrode 23a and the contact plug 30a is ensured by the side wall film 24a.

In the semiconductor substrate 11 directly below the side wall film 24a, an N ^- type diffusion layer 26a having a low impurity concentration called LDD is formed. That is, the LDD length of the normal transistor is substantially equal to the thickness of the sidewall film 24a. Adjacent to the N ⁻ type diffusion layer 26a, the N ⁻ type diffusion layer 26
An N ⁺ type diffusion layer 27a having an impurity concentration higher than a is formed. MISFET on the semiconductor substrate 11
Is formed to completely cover the substrate.

The interlayer insulating film 28 includes an N ⁺ type diffusion layer 27a.
Is formed. The contact hole 29a may or may not overlap with the side wall film 24a. Similarly, the contact hole 29a is formed in the gate electrode 2
3a may or may not overlap. The sidewall film 25a does not exist in the contact hole 29a.

In the contact hole 17, a contact plug 30a made of, for example, tungsten (W) is formed. A metal wiring 31a is formed on the contact plug 30a. On the interlayer insulating film 28, an interlayer insulating film 34 that completely covers the metal wiring 31a is formed.

Next, the configuration of the high breakdown voltage transistor in the peripheral circuit section will be described. A gate insulating film 22b is formed on a P-type semiconductor substrate (may be a well region) 21, and a gate electrode 23b is formed on the gate insulating film 22b. A cap insulating film 32b is formed on the gate electrode 23b. Side walls are formed on the side walls of the gate electrode 23b and the cap insulating film 32b.

The sidewall has two types of sidewall films 24b and 25b made of different materials. The sidewall film 24b is disposed adjacent to the gate electrode 23b and the cap insulating film 32b, and is made of a material having an etching selectivity with respect to the interlayer insulating film 28. When the interlayer insulating film 28 is made of a silicon oxide film, the sidewall film 24b is made of, for example, a silicon nitride film.
The side wall film 25b is disposed adjacent to the side wall film 24b, and is made of a material having substantially the same etching rate as the interlayer insulating film 28. The sidewall film 25b is made of, for example, the same material (for example, a silicon oxide film) as the interlayer insulating film 28.

In the high-breakdown-voltage transistor, a sufficient margin is provided between the gate electrode 23b and the contact hole 29b so that the contact hole 29b does not overlap with any of the gate electrode 23b and the sidewall films 24b and 25b. ing. That is, the self-aligned contact technology is not applied to the high breakdown voltage transistor.

Semiconductor substrate 1 immediately below sidewall films 24b and 25b
1 has a low impurity concentration called LDD.
^A- type diffusion layer 26b is formed. That is, the LDD length of the high breakdown voltage transistor is longer than the LDD length of the normal transistor by the thickness of the sidewall film 25b. Further, adjacent to the N ⁻ type diffusion layer 26b, the N ⁻ type diffusion layer 26
An N ⁺ type diffusion layer 27b having an impurity concentration higher than b is formed.

On the semiconductor substrate 11, an interlayer insulating film 28 that completely covers the MISFET is formed. In the interlayer insulating film 28, a contact hole 29b reaching the N ⁺ type diffusion layer 27b is formed. Contact hole 29b
Are formed so as not to overlap with the side wall films 24b and 25b.

In the contact hole 17, a contact plug 30b made of, for example, tungsten (W) is formed. A metal wiring 31b is formed on the contact plug 30b. On the interlayer insulating film 28, an interlayer insulating film 34 that completely covers the metal wiring 31b is formed.

Next, the configuration of the memory cells in the memory cell section will be described. A gate insulating film 22c is formed on a P-type semiconductor substrate (may be a well region) 21, and a floating gate electrode 2 is formed on the gate insulating film 22c.
3Ac is formed. Floating gate electrode 2
An insulating film (for example, a so-called ONO film) 3
3, a control gate electrode 23Bc is formed.

On the control gate electrode 23Bc,
A cap insulating film 32c functioning as a mask when forming the contact hole 29c is formed. Floating gate electrode 23Ac, control gate electrode 23
Side walls are formed on the side walls of Bc and the cap insulating film 32c.

The sidewall has two types of sidewall films 24c and 25c made of different materials. The side wall film 24c is formed of the floating gate electrode 23A.
c, is disposed adjacent to the control gate electrode 23Bc and the cap insulating film 32c, and is made of a material having an etching selectivity with respect to the interlayer insulating film 28. That is, the sidewall film 24c is made of a material that is hardly etched when the contact hole 29c is formed, for example, a silicon nitride film when the interlayer insulating film 28 is made of a silicon oxide film.

The side wall film 25c is disposed adjacent to the side wall film 24c, and is made of a material having substantially the same etching rate as the interlayer insulating film 28. That is, the side wall film 25
c is made of a material that is etched together with the interlayer insulating film 28 when the contact hole 29c is formed, for example, the same material as the interlayer insulating film 28 (for example, a silicon oxide film).

The side wall film 25c may be made of either a conductor or an insulator.
Is preferably made of an insulator. Each gate electrode 23
This is to ensure insulation between Ac, 23Bc and contact plug 30c. In the portion where the contact hole 29c is formed, the side wall film 25c does not exist.
At least the sidewall film 24c exists. That is, the insulation between the gate electrodes 23Ac and 23Bc and the contact plug 30c is ensured by the side wall film 24c.

In the semiconductor substrate 11 including immediately below the side wall films 24c and 25c, a diffusion layer 26c having a low impurity concentration is provided.
N, 26cP and diffusion layer 27c having high impurity concentration
Are formed. The drain of the memory cell is N
⁺ Diffusion layer 27c and P ⁻ diffusion layer 26cP, and the source is composed of N ⁺ diffusion layer 27c and N ⁻ diffusion layer 26cN.

On the semiconductor substrate 11, an interlayer insulating film 28 that completely covers the MISFET is formed. A contact hole 29 reaching the diffusion layer 27c is formed in the interlayer insulating film 28.
c is formed. The contact hole 29c is formed in the side wall film 2
4c may or may not overlap. Similarly, contact hole 29
c overlaps with the control gate electrode 23Bc and the floating gate electrode 23Ac,
Conversely, they do not have to overlap. The sidewall film 25c is not disposed in the contact hole 29c.

In the contact hole 29c, for example,
A contact plug 30c made of tungsten (W) is formed. The metal wiring 31c is formed on the contact plug 30c. On the interlayer insulating film 28,
An interlayer insulating film 34 that completely covers the metal wiring 31c is formed.

According to the semiconductor device having the above structure, M
Sidewalls made of two different materials are formed on the side walls of the gate electrode of the ISFET. That is, the side walls are formed of side wall films 24a, 24b, 24c having an etching selectivity with respect to the interlayer insulating film 28,
It is composed of side wall films 25a, 25b, and 25c having substantially the same etching rate as the interlayer insulating film.

In a normal transistor operating at a low voltage, a side wall film 24a exists between the gate electrode 23a and the contact hole 29a.
Does not exist. Naturally, both sidewall films 24a and 25a exist around the gate electrode 23a except between the gate electrode 23a and the contact hole 29a. In a normal transistor, a diffusion layer 26a functioning as an LDD is formed only immediately below the sidewall film 24a.

Therefore, in a peripheral circuit portion including a normal transistor operating at a low voltage, the area occupied by the normal transistor can be reduced by the self-aligned contact technique without increasing the contact resistance. In a normal transistor, a short LDD further reduces
The degree of integration of the LSI can be improved.

In a high breakdown voltage transistor operating at a high voltage, the contact hole 29b is formed in the side wall film 2
4b and 25b do not overlap.
Further, a diffusion layer 26b functioning as an LDD is formed immediately below the sidewall films 24b and 25b.

Therefore, in a peripheral circuit composed of a high breakdown voltage transistor operating at a high voltage, the breakdown voltage of the drain diffusion layer of the high breakdown voltage transistor is set to, for example, 10 V due to the long LDD.
The above can be secured.

In the memory cell of the memory cell portion, the side wall film 24c exists between the floating gate electrode 23Ac and the control gate electrode 23Bc and the contact hole 29c, and the side wall film 25c does not exist. In other portions than between the floating gate electrode 23Ac and the control gate electrode 23Bc and the contact hole 29c, both the side wall films 24c and 25c remain.

Therefore, in the memory cell portion, the self-aligned contact technology allows the contact resistance to be increased without increasing the contact resistance.
It is possible to reduce the area occupied by the memory cells of the flash EEPROM.

As described above, when the MISFET whose integration degree is to be improved by the self-aligned contact technique and the MISFET whose drain withstand voltage of the drain diffusion layer is desired to be sufficiently formed are formed on the same substrate, the improvement of the integration degree of the LSI It is possible to simultaneously improve the drain withstand voltage of the withstand voltage transistor.

Although the above-described semiconductor device has been described with reference to an N-channel MISFET, it is apparent that the present invention can be applied to a P-channel MISFET. Next, a method of manufacturing the flash EEPROM shown in FIGS. 2 and 3 will be described.

First, as shown in FIG. 4, a gate electrode 23a of a normal transistor and a gate electrode 23b of a high voltage transistor in a peripheral circuit portion are formed, and a floating gate electrode 23Ac and a control gate of a memory cell in a memory cell portion are formed. The electrode 23Bc is formed.

Here, as a method of forming the gate electrodes 23a and 23b, the floating gate electrode 23Ac, and the control gate electrode 23Bc, a known technique is applied. For example, in the peripheral circuit section, after forming each layer, PE
By performing P and RIE, gate electrodes 23a and 23b are formed. In the memory cell portion, a first layer of polysilicon is formed, a slit is formed, a second layer of polysilicon is formed, and then PEP and RIE are performed to form a floating gate electrode 23Ac and a control gate. The electrode 23Bc is formed.

Incidentally, 22a to 22c are gate insulating films (for example, silicon oxide films), 33 is an insulating film (for example, so-called ONO film), and 32a to 32c are cap insulating films (for example, silicon nitride film). is there.

Next, as shown in FIG. 5, thermal oxidation is performed,
An oxide film 35 is formed on each of the surfaces of the P-type semiconductor substrate 21, the gate electrodes 23a and 23b, the floating gate electrode 23Ac, and the control gate electrode 23Bc.
Thereafter, an ion implantation step is performed.

Normal transistors in the peripheral circuit section (for example,
For an N-channel MISFET constituting a CMOS circuit operating at 2.5 V, phosphorus (P) and arsenic (As) are ion-implanted by self-alignment using the gate electrode 23a as a mask in order to form an LDD. I do. The dose of arsenic is suitably 1 × 10 ¹⁴ cm ⁻² or more, and the dose of phosphorus is preferably a value that is about one digit smaller than the dose of arsenic. These impurities are activated by an annealing step performed later, and become the diffusion layer 26a.

For a high withstand voltage transistor in the peripheral circuit portion (for example, an N-channel MISFET having a drain withstand voltage of 10 V or more constituting a circuit for driving a memory cell), the gate electrode 23b is masked in order to form an LDD. Then, phosphorus (P) is ion-implanted by self-alignment. At this time, the dose of phosphorus is lower than that of a normal transistor, for example, about 5 × 10 ¹³ cm ⁻² . This impurity is activated by an annealing step performed later, and becomes the diffusion layer 26b.

The memory cells (eg, NO
For each memory cell of the R-type flash EEPROM, ion implantation for forming a source diffusion layer and a drain diffusion layer is performed. For example, arsenic and phosphorus are ion-implanted into a source diffusion layer, and arsenic and boron (B) are ion-implanted into a drain diffusion layer. These impurities are activated by an annealing step performed later, and become the source diffusion layers 26cN and 27c and the drain diffusion layers 26cP and 27c.

Next, as shown in FIG. 6, a silicon nitride film (a material having an etching selectivity with respect to the interlayer insulating film) is formed on the entire surface of the semiconductor substrate 21 by using the LPCVD method.
24 is formed with a thickness T1 (for example, about 100 nm). Thereafter, the silicon nitride film 24 is etched back by using the RIE method.

As a result, as shown in FIG. 7, a side wall film 24a is formed on the side wall of the gate electrode 23a of the normal transistor in the peripheral circuit portion, and on the side wall of the gate electrode 23b of the high breakdown voltage transistor in the peripheral circuit portion. , Sidewall film 24b is formed, and floating gate electrode 23A in the memory cell portion is formed.
A sidewall film 24c is formed on the sidewalls of the gate electrode c and the control gate electrode 23Bc.

The thickness T1 of the silicon nitride film 24 is
It becomes almost equal to the thickness (width) of the side wall films 24a, 24b, 24c. Next, as shown in FIG. 8, a resist pattern 36 is formed on the semiconductor substrate 21 to form a diffusion layer having a high impurity concentration for the normal transistor in the peripheral circuit portion. The resist pattern 36 is formed so as to have an opening only in a peripheral circuit portion where a transistor is usually formed.

Then, the gate electrode 23a and the side wall film 24a
Using the resist pattern 36 as a mask and self-alignment, arsenic is ion-implanted at a dose of about 5 × 10 ¹⁵ cm ⁻² . Thereafter, the resist pattern 36 is removed. This impurity is activated by an annealing step performed later, and becomes the diffusion layer 27a.

Therefore, the normal transistor in the peripheral circuit portion has the LDD length equal to the thickness T1 of the side wall film 24a (for example, 10
0 nm) and high performance MI with small parasitic resistance
It becomes an SFET.

Next, as shown in FIG. 9, a silicon oxide film (a material having the same etching rate as that of the interlayer insulating film) is formed on the entire surface of the semiconductor substrate 21 by the LPCVD method to a thickness T2 (for example, (About 100 nm).

Thereafter, when the silicon oxide film is etched back by using the RIE method, a sidewall film 25a is formed on the sidewall of the sidewall film 24a of the normal transistor in the peripheral circuit portion, and the high breakdown voltage transistor of the peripheral circuit portion is formed. A sidewall film 25b is formed on a sidewall of the sidewall film 24b, and a sidewall film 25c is formed on a sidewall of the sidewall film 24c of the memory cell in the memory cell portion.

Note that the thickness T2 of the silicon oxide film is substantially equal to the thickness (width) of the side wall films 25a, 25b, 25c. Alternatively, phosphorus may be doped in the silicon oxide film to reduce the influence of mobile ions in the silicon oxide film.

Next, as shown in FIG. 10, a resist pattern 37 is formed on the semiconductor substrate 21 to form a diffusion layer having a high impurity concentration for the high breakdown voltage transistor in the peripheral circuit portion. This resist pattern 37
Is formed so as to have an opening only in the peripheral circuit portion where the high breakdown voltage transistor is formed.

Then, the gate electrode 23b and the side wall film 24 are formed.
b, 25b and the resist pattern 37 as a mask,
Arsenic dose of 5 × 10 ¹⁵ cm by self-alignment
Ion implantation at about ^-2 . After that, resist pattern 3
7 is removed. This impurity is activated by an annealing step performed later, and becomes the diffusion layer 27b.

Therefore, the high breakdown voltage transistor in the peripheral circuit portion has the LDD length equal to the thickness T1 + T2 of the side wall films 24b and 25b.
(For example, 200 nm) and a high-performance MISFET having a drain withstand voltage of 10 V or more.

Next, as shown in FIG. 11, an interlayer insulating film 28 covering the memory cell and the MISFET is formed on the entire surface of the semiconductor substrate 21 by using the LPCVD method. The interlayer insulating film 28 is composed of, for example, a silicon oxide film (BPSG film) containing boron and phosphorus. Thereafter, the surface of the interlayer insulating film 28 is flattened using a flattening process (for example, a CMP process).

A resist pattern 38 is formed on interlayer insulating film 28 by PEP. Resist pattern 3
Reference numeral 8 includes a contact hole pattern for the drain diffusion layer of the memory cell and a contact hole pattern for the diffusion layer of the MISFET in the peripheral circuit portion.

In the normal transistor of the peripheral circuit portion,
The designed space between the opening 38a of the resist and the gate electrode 23a is, for example, about 100 nm (the thickness T of the side wall film 24a).
1). In the high breakdown voltage transistor in the peripheral circuit portion, the opening 38b of the resist and the gate electrode 23
The design interval of b is set to T (= T1 + T2 + α).
Here, α is a margin in consideration of misalignment during photolithography. In the memory cell of the memory cell portion, the designed space between the resist opening 38c and the control gate electrode 23Bc is, for example, about 100 nm.
(About the same as the thickness T1 of the sidewall film 24c).

Then, using the resist pattern 38 as a mask, the interlayer insulating film 28 is etched by RIE.
Thereafter, the resist pattern 38 is removed. As a result, as shown in FIG. 12, contact holes 29a, 29b, and 29c are formed in the interlayer insulating film.

In the normal transistor in the peripheral circuit portion, even if the resist opening 38a is shifted by about 100 nm toward the gate electrode 23a due to misalignment at the time of photolithography, since the side wall film 24a exists, the contact hole 29a The gate electrode 23a is never exposed.

On the other hand, since the side wall film 25a has the same etching rate as the interlayer insulating film 28, it is almost completely removed. That is, the area (contact area) of the semiconductor substrate 21 exposed on the bottom surface of the contact hole 29a is increased, so that the contact resistance is reduced.

In the high breakdown voltage transistor in the peripheral circuit portion, even if the resist opening 38b is displaced by about 100 nm toward the gate electrode 23b due to misalignment during photolithography, a margin α for misalignment is secured in advance. Therefore, the sidewall films 24b and 25b are not etched.

In the memory cell of the memory cell portion, even if the resist opening 38c is shifted by about 100 nm toward the gate electrode 23c due to misalignment at the time of photolithography, the side wall film 24c is still present. The floating gate electrode 23Ac and the control gate electrode 23Bc are not exposed.

On the other hand, since the side wall film 25c has the same etching rate as the interlayer insulating film 28, it is almost completely removed. That is, the area (contact area) of the semiconductor substrate 21 exposed on the bottom surface of the contact hole 29c is increased, so that the contact resistance is reduced.

Next, as shown in FIG. 13, contact plugs 30a, 30b, 30c made of, for example, tungsten are formed in the contact holes 29a, 29b, 29c. Specifically, the contact plugs 30a, 30
b and 30c are filled only in the contact holes 29a, 29b and 29c by applying the CVD method and the CMP method.

Contact plugs 30a, 30b, 30c
The metal wirings 31a, 31b, 31c are formed on the upper side. On the interlayer insulating film 28, furthermore, metal wirings 31a,
An interlayer insulating film 34 covering 31b and 31c is formed.

In this embodiment, the boundary between the sidewalls made of two different materials and the boundary between the two kinds of diffusion layers are described as being substantially the same.
In the present invention, there is no problem if the diffusion layer having a high concentration is extended at the time of activation by the thermal process so that the two boundaries do not completely coincide with each other.

[0109]

As described above, according to the semiconductor device of the present invention, the following effects can be obtained. MISFET
Side walls made of two different materials are formed on the side walls of the gate electrode. That is, the sidewall is composed of a first sidewall film having an etching selectivity with respect to the interlayer insulating film and a second sidewall film having substantially the same etching rate as the interlayer insulating film.

In a normal transistor operating at a low voltage, the first sidewall film exists between the gate electrode and the contact hole, and the second sidewall film does not exist. Further, a diffusion layer functioning as an LDD is formed only immediately below the first side wall film.

Therefore, it is possible to improve the integration degree of the LSI without increasing the contact resistance by the self-aligned contact and the short LDD. In a high-breakdown-voltage transistor operating at a high voltage, the contact hole does not overlap with any of the first and second sidewall films. Further, a diffusion layer functioning as an LDD is formed immediately below the first and second sidewall films.

Therefore, with the long LDD, the withstand voltage of the drain diffusion layer of the high withstand voltage transistor can be maintained at 10 V or more. Further, in the memory cell of the memory cell portion, the first sidewall film exists between the floating gate electrode and the control gate electrode and the contact hole, and the second sidewall film does not exist. Further, a diffusion layer functioning as an LDD is formed only immediately below the first side wall film.

Therefore, the self-aligned contact can increase the degree of integration of the memory cell array without increasing the contact resistance. As described above, it is desirable to improve the integration degree by the self-aligned contact technology.
In the case where an ISFET (including a memory cell) and a MISFET for which a sufficient withstand voltage of a diffusion layer is to be formed on the same substrate, the integration degree of an LSI (or a memory cell array) can be improved without increasing contact resistance and a high withstand voltage transistor Of the drain withstand voltage can be simultaneously improved.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a plan view showing a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a sectional view taken along the line III-III in FIG. 2;

FIG. 4 is a sectional view showing one step of a method of manufacturing the semiconductor device of FIGS. 2 and 3;

FIG. 5 is a sectional view showing one step of a method of manufacturing the semiconductor device of FIGS. 2 and 3;

FIG. 6 is a sectional view showing one step of a method of manufacturing the semiconductor device in FIGS. 2 and 3;

FIG. 7 is a sectional view showing one step of a method of manufacturing the semiconductor device in FIGS. 2 and 3;

FIG. 8 is a sectional view showing one step of a method of manufacturing the semiconductor device of FIGS. 2 and 3;

FIG. 9 is a sectional view showing one step of a method of manufacturing the semiconductor device in FIGS. 2 and 3;

FIG. 10 is a sectional view showing one step of a method of manufacturing the semiconductor device in FIGS. 2 and 3;

FIG. 11 is a sectional view showing one step of a method of manufacturing the semiconductor device in FIGS. 2 and 3;

FIG. 12 is a sectional view showing one step of a method of manufacturing the semiconductor device in FIGS. 2 and 3;

FIG. 13 is a sectional view showing one step of a method of manufacturing the semiconductor device of FIGS. 2 and 3;

FIG. 14 is a cross-sectional view illustrating a conventional semiconductor device.

FIG. 15 is a cross-sectional view illustrating a conventional semiconductor device.

FIG. 16 is a cross-sectional view illustrating a conventional semiconductor device.

FIG. 17 is a cross-sectional view illustrating a problem of a conventional semiconductor device.

FIG. 18 is a cross-sectional view illustrating a conventional semiconductor device.

FIG. 19 is a cross-sectional view illustrating a problem of a conventional semiconductor device.

[Explanation of symbols]

11, 21: semiconductor substrate, 12, 22a, 22b, 22c: gate insulating film, 13, 23a, 23b: gate electrode, 14: sidewall insulating film, 15a, 26a, 26b, 26c: low concentration diffusion layer (L
DD), 15b, 27a, 27b, 27c: high concentration diffusion layer, 16, 28, 34: interlayer insulating film, 17, 29a, 29b, 29c: contact hole, 18, 30a, 30b, 30c: contact plug, 19, 31a, 31b, 31c: metal wiring, 20, 32a, 32b, 32c: cap insulating film, 23Ac: floating gate electrode, 23Bc: control gate electrode, 24a, 24b, 24c: first side wall film, 25a, 25b, 25c: Second sidewall film, 33: insulating film (ONO)
Film), 35: oxide film, 36, 37, 38: resist pattern.

Claims (15)

[Claims] 1. A MISFET formed on a semiconductor substrate
And the MISFET formed on the MISFET
A semiconductor device having an interlayer insulating film having a contact hole reaching the diffusion layer of the MISFET, a sidewall of the gate electrode of the MISFET is adjacent to the gate electrode, and is etched more than the interlayer insulating film when the contact hole is opened. A first side wall film having a substantially lower speed and a second side wall film adjacent to the first side wall film and having an etching speed substantially higher than the first side wall film are arranged; Wherein the second side wall film is removed. 2. The MISFET has a first diffusion layer and a second diffusion layer having a higher impurity concentration than the first diffusion layer, wherein the first diffusion layer is located immediately below the first side wall film. The semiconductor device according to claim 1, wherein the semiconductor device is arranged corresponding to the following. 3. The semiconductor device according to claim 1, wherein a cap insulating film having substantially the same etching rate as the first sidewall film is disposed on the gate electrode. 4. The semiconductor device according to claim 1, wherein said second sidewall film has substantially the same etching rate as said interlayer insulating film. 5. The method according to claim 1, wherein the first side wall film remains at an opening of the contact hole.
13. The semiconductor device according to claim 1. 6. A semiconductor device comprising: a memory cell having a stacked gate electrode formed on a semiconductor substrate; and an interlayer insulating film formed on the memory cell and having a contact hole reaching a diffusion layer of the memory cell. In the first aspect, a first side wall of the stacked gate electrode of the memory cell is adjacent to the stacked gate electrode and has a substantially lower etching rate than the interlayer insulating film when the contact hole is opened.
A side wall film and a second side wall film adjacent to the first side wall film and having an etching rate substantially higher than that of the first side wall film are disposed, and the second side wall film is removed at an opening of the contact hole. A semiconductor device characterized by being performed. 7. The semiconductor device according to claim 6, wherein a cap insulating film having substantially the same etching rate as the first side wall film is disposed on the stacked gate electrode. 8. The semiconductor device according to claim 6, wherein said second side wall film has substantially the same etching rate as said interlayer insulating film. 9. The method according to claim 6, wherein the first side wall film remains in an opening of the contact hole.
13. The semiconductor device according to claim 1. 10. A first MISFET and a first MISFE
And a second MISFET operating at an operating voltage higher than T.
The ET includes a first diffusion layer and a second diffusion layer having a higher impurity concentration than the first diffusion layer.
And a first side wall film adjacent to the gate electrode and a second side wall film adjacent to the first side wall film are disposed on side walls of the gate electrode of the second MISFET, respectively.
The first diffusion layer of the SFET is disposed directly below the first sidewall film, and the first diffusion layer of the second MISFET is disposed directly below the first and second sidewall films. A semiconductor device characterized in that: 11. An interlayer insulating film having a first contact hole reaching a second diffusion layer of the first MISFET and a second contact hole reaching a second diffusion layer of the second MISFET, on the first and second MISFETs. Is formed, and the distance from the gate electrode of the second MISFET to the second contact hole is equal to the first MISFE.
11. The semiconductor device according to claim 10, wherein the distance is longer than a distance from the gate electrode of T to the first contact hole. 12. The first side wall film includes the first and second side walls.
12. The method according to claim 11, wherein an etching rate at the time of opening the contact hole is substantially lower than that of the interlayer insulating film, and the etching rate of the second sidewall film is substantially higher than that of the first sidewall film. Semiconductor device. 13. A cap insulating film having substantially the same etching rate as the first side wall film is disposed on the gate electrodes of the first and second MISFETs. Semiconductor device. 14. The semiconductor device according to claim 12, wherein said second side wall film has substantially the same etching rate as said interlayer insulating film. 15. The method according to claim 15, wherein the first sidewall film is present between the gate electrode of the first MISFET and the first contact hole, and the second sidewall film is not present.
13. The semiconductor device according to claim 12, wherein the first and second sidewall films are present between the gate electrode of T and the second contact hole.