JPH1084052A - Semiconductor integrated circuit device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a structure and a manufacturing method capable of forming an AND type flash memory at high density. SOLUTION: A first layer polycrystalline silicon film 2 as the lower floating gate electrode of a floating gate electrode is formed on a semiconductor substrate and after the formation of a drain 5 and a souce 6 by ion implanting process using the silicon film 2 as a mask, selective oxide films 8 are formed by selective thermal oxidizing process on the upper layer of the drain 5 and the source 6. Later, the second polycrystalline silicon sidewall 10 made of a PAD oxide film 9, polycrystalline silicon and the third layer polycrystalline silicon film as an upper floating gate electrode of the floating gate electrode are formed and then the third layer polycrystalline silicon film, the selective oxide films 8 and the semiconductor substrate are etched away using the same mask to form an isolation so that a buried part made of silicon oxide film may be formed into an element isolation structure.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly to a technique effective when applied to an AND-type batch erasing nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art An AND-type batch erasing nonvolatile semiconductor memory device (AND-type flash memory) is composed of a plurality of storage MOSFETs and switch MOSFETs as described in, for example, Japanese Patent Application Laid-Open No. 7-176705. In this memory cell block, the source of each storage MOSFET is shared by a sub-bit line formed by a buried diffusion layer wiring and connected to one of the source / drain of the switch MOSFET. The drain is also shared by the sub-bit line formed by the buried diffusion layer wiring and has a structure connected to one of the source and the drain of the switch MOSFET. That is, there is provided an AND-type electrically collectively erasing EEPROM in which memory cells are connected in parallel to the sub-bit lines.

[0003] Individual storage MOSFETs are formed on an active region surrounded by a field insulating film on a semiconductor substrate.
A lower floating gate electrode and an upper floating gate electrode,
The floating gate electrode has a T-shaped cross section, a control gate electrode formed on the floating gate electrode via an interlayer insulating film, and a source and a drain as the sub-bit lines. The control gate electrode functions as a word line of the memory cell, extends in a direction perpendicular to the sub-bit line, and is shared by different memory cell blocks.

A memory gate insulating film is formed between the lower floating gate electrode and the semiconductor substrate, and information is written or erased in a memory cell by a tunnel current passing through the memory gate insulating film.

In order to insulate the upper floating gate electrode from the sub-bit line of the semiconductor substrate, a sidewall made of a silicon oxide film is formed on the side surface of the lower floating gate electrode, and a selective oxide film is formed between the sidewall and the field insulating film. Are formed.

[0006]

However, the above AN
In the method of manufacturing a D-type flash memory, at least three photolithography steps using three masks must be performed in order to perform processing in a direction parallel to the sub-bit lines in the memory cell block. That is, a process for forming a field oxide film, a process for processing a lower floating gate electrode that is a first floating gate electrode,
And a process for processing an upper floating gate electrode which is a second-layer floating gate electrode.

In the above-described method of manufacturing an AND type flash memory, selective thermal oxidation is performed on a buried diffusion layer wiring by a selective oxidation method in order to insulate a sub-bit line serving as a buried diffusion layer wiring from an upper floating gate electrode. Although the film is formed as described above, at this time, misalignment of the mask for forming the field oxide film and the lower floating gate electrode occurs inevitably. The area of the upper selective oxide film formation region changes. For example, if one of them (for example, the source region) becomes wider,
The other (for example, the drain region) becomes narrower. As a result, a situation occurs in which a thick selective oxide film is formed when the formation region is wide, and a selective oxide film is hardly formed when the formation region is extremely narrow. That is, the thickness of the selective oxide film formed on the buried diffusion layer wiring varies.

When the variation in the thickness of the selective oxide film on the buried diffusion layer wiring becomes large, there arises a problem that the processing margin of the memory cell decreases and a problem that the device characteristics of the memory cell vary widely.

In order to avoid the above problem, it is difficult to reduce the area of the memory cell if an attempt is made to secure a margin for misalignment between the field oxide film and the lower floating gate electrode.

In the above-described method of manufacturing an AND type flash memory, a side wall made of a silicon oxide film is formed on the side wall of the lower floating gate electrode. Due to the heat treatment at the time of forming the film, bird's beak grows in the memory gate insulating film below the lower floating gate electrode, causing a problem of increasing the thickness of the memory gate insulating film. As a countermeasure, formation of a sidewall with a silicon nitride film has been studied.

In the above-described manufacturing method using the silicon nitride film sidewall, a step of forming a CVD-oxide film as a replacement of the sidewall portion can be considered.
-At the time of dry etching when forming a sidewall with an oxide film, there is a problem that a dry etch margin is limited because the material is the same as a selective oxide film which is a lower layer material of a CVD-oxide film.

Further, in the above-mentioned AND type flash memory, the operation of writing information is performed at the edge portion of the lower floating gate electrode, and in such a case, sufficient impurity active region is provided below the edge portion. If the impurity of the concentration is not introduced, a reliable writing operation cannot be performed. However, if the impurity concentration of the impurity semiconductor region is increased, a problem of short-circuit between channels or punch-through occurs, and the impurity concentration cannot be increased to a certain level or more.

An object of the present invention is to reduce the number of masks for performing processing in a direction parallel to a sub-bit line in a memory cell block and to simplify a manufacturing process of a semiconductor integrated circuit device.

Another object of the present invention is to provide a structure of a semiconductor integrated circuit device capable of making the thickness of a selective oxide film formed on a buried diffusion layer wiring uniform, and a method of manufacturing the same. .

Another object of the present invention is to provide a technique capable of stabilizing the device characteristics of a memory cell and coping with high integration.

Another object of the present invention is to provide a technique capable of avoiding deterioration of device characteristics due to a decrease in an etch margin with respect to a selective oxide film when forming a silicon oxide film sidewall.

Another object of the present invention is to provide a technique capable of securing a margin for punch-through or short-circuiting between channels and reliably performing an information writing operation.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0019]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A semiconductor integrated circuit device according to the present invention comprises a floating gate electrode having a lower floating gate electrode and an upper floating gate electrode formed on a main surface of a semiconductor substrate via a first gate insulating film; A selective oxide layer formed on the side of the floating gate electrode, formed below the upper floating gate electrode, and a channel region formed on the main surface of the semiconductor substrate below the first gate insulating film; An impurity semiconductor region functioning as a source or a drain of a MISFET formed under the selective oxidation layer and a part of the lower portion of the first gate insulating film, and a control formed over the upper floating gate electrode via an interlayer insulating film. A nonvolatile memory cell including a gate electrode and a plurality of nonvolatile memory cells connected in parallel by an impurity semiconductor region shared by the plurality of nonvolatile memory cells. A semiconductor integrated circuit device comprising a D-type nonvolatile memory cell block, wherein a control gate electrode extends to a plurality of nonvolatile memory cell blocks and is shared by nonvolatile memory cells in different nonvolatile memory cell blocks The nonvolatile memory cell block is electrically insulated by an element isolation structure composed of a buried silicon oxide film buried in a trench structure.

According to such a semiconductor integrated circuit device,
Since the nonvolatile memory cell block is electrically insulated by the element isolation structure composed of the buried silicon oxide film buried in the trench structure, it is not necessary to form a field insulating film, and therefore, it is not necessary to form a field insulating film. No boundary region with the selective oxide film is formed. As a result, it is possible to avoid device failure due to a decrease in the thickness of the insulating film, which is likely to occur in such a boundary region, and to improve the reliability and yield of the semiconductor integrated circuit device.

Further, in the semiconductor integrated circuit device of the present invention,
As described above, since the boundary region between the field insulating film and the selective oxide film is not formed, the silicon nitride film can be used as the sidewall of the lower floating gate electrode. As a result, when the silicon oxide film sidewall is used. Is prevented, and device characteristics of the memory cell can be improved.

(2) The semiconductor integrated circuit device according to the present invention is the semiconductor integrated circuit device according to the above (1), wherein the floating gate electrode is a lower floating gate electrode, an upper floating gate electrode,
And a first sidewall formed between the lower floating gate electrode and the selective oxidation layer, wherein the first sidewall is formed on the main surface of the semiconductor substrate via a second gate insulating film through a polycrystalline silicon. It consists of

According to such a semiconductor integrated circuit device,
The floating gate electrode includes a lower floating gate electrode, an upper floating gate electrode, and a first sidewall formed between the lower floating gate electrode and the selective oxide layer, and the first sidewall is formed of a main portion of the semiconductor substrate. Since polycrystalline silicon is formed on the second gate insulating film on the surface, a dry etch margin for forming the first sidewall can be improved.

That is, the silicon oxide film sidewall of the lower floating gate electrode used in the conventional process is changed to a silicon nitride film sidewall, and the silicon nitride film sidewall is removed as a re-attached sidewall after removal of the silicon nitride film sidewall. Instead of a silicon oxide film formed by a method, a polycrystalline silicon film is adopted. By employing a polycrystalline silicon film, it is possible to secure an etching selectivity with a selective oxide film as a base during dry etching at the time of forming a sidewall, and to obtain a dry etching margin.

It is needless to say that the second gate insulating film formed below the polycrystalline silicon sidewall is for securing insulation between the semiconductor substrate and the floating gate electrode.

(3) The semiconductor integrated circuit device according to the present invention is the semiconductor integrated circuit device according to (2), wherein the operation of recording information in the nonvolatile memory cell is performed by a tunnel passing through the second gate insulating film. It is performed by current.

According to such a semiconductor integrated circuit device,
Since the operation of recording information in the nonvolatile memory cell is performed by a tunnel current passing through the second gate insulating film, the information can be reliably recorded and the problem of punch-through or short-circuit between channels can be dealt with.

That is, since the entire region of the second gate insulating film is formed above the impurity semiconductor region, the impurity concentration of the impurity semiconductor region thereunder is unnecessarily increased to reach the lower portion of the first gate insulating film. There is no need to diffuse the impurity semiconductor region. Therefore, the impurity concentration of the impurity semiconductor region can be reduced to a concentration effective for preventing punch-through, and the channel region is sufficiently formed below the first gate insulating film sandwiched between the second gate insulating films. Since a short gate length is ensured, no short circuit occurs between channels.

(4) The method of manufacturing a semiconductor integrated circuit device according to the above (1), (2) or (3), wherein a selective oxide film is formed on the impurity semiconductor region. After the formation, the trench structure is processed in the central portion of the selective oxide film and the impurity semiconductor region to form an element isolation structure.

According to such a method of manufacturing a semiconductor integrated circuit device, after a selective oxide film is formed on an impurity semiconductor region, a trench structure is formed in a central portion of the selective oxide film and the impurity semiconductor region to form an element isolation structure. Is formed, the thickness of the selective oxide film can be made uniform irrespective of the presence or absence of a shift between the mask for forming the lower floating gate electrode and the mask for forming the element isolation structure.

That is, as described above, in the conventional manufacturing method, the thickness of the selective oxide film is different due to misalignment between the mask of the lower floating gate electrode and the mask of the field insulating film. However, in the manufacturing method of the present invention, since the selective oxidation layer is formed before the element isolation structure is formed, the occurrence of the mask shift causes a shift in the position of the groove structure formed in the selective oxidation layer. And no difference in the thickness of the selective oxidation layer can occur.

As a result of making the thickness of the selective oxide film uniform, it is possible to secure a processing margin for the memory cell and to reduce variations in device characteristics of the memory cell. Further, since it is not necessary to secure a margin for mask alignment between the lower floating gate electrode and the element isolation structure, it is possible to reduce the size of the memory cell.

Note that the selective oxidation layer is formed between the sidewalls of the lower floating gate electrode formed before the step, and the lower floating gate electrode is formed by one mask. Since no mask is used to form the sidewalls, the spacing between the sidewalls of each lower floating gate electrode is uniform, and the thickness of the selective oxide film formed there is uniform.

(5) The semiconductor integrated circuit device according to the present invention is the method for manufacturing a semiconductor integrated circuit device according to the above (4), wherein the impurity semiconductor region of the upper floating gate electrode is formed in the same step as the processing of the groove structure. This is for processing the end side in the direction parallel to.

According to such a method of manufacturing a semiconductor integrated circuit device, the edge of the upper floating gate electrode in the direction parallel to the impurity semiconductor region is processed in the same step as the processing of the groove structure. The number of masks can be reduced by one in comparison. That is, the element isolation structure and the upper floating gate electrode, which are conventionally formed in separate processes, are processed in the same process, and the mask is shared and reduced. Thus, the manufacturing process of the semiconductor integrated circuit device can be simplified, the manufacturing cost can be reduced, the yield can be improved, and the reliability can be improved.

(6) The semiconductor integrated circuit device according to the present invention is the method for manufacturing a semiconductor integrated circuit device according to the above (4) or (5), wherein the nonvolatile memory cells are arranged simultaneously with the formation of the element isolation structure. To form an element isolation structure in a peripheral circuit region other than the memory cell region.

According to such a method of manufacturing a semiconductor integrated circuit device, the element isolation structure is formed in the peripheral circuit region other than the memory cell region in which the nonvolatile memory cells are arranged, simultaneously with the formation of the element isolation structure. The process can be further simplified, the manufacturing cost can be reduced, the yield can be improved, and the reliability can be improved.

[0039]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

FIGS. 1 to 14 are a top view and a sectional view, respectively, showing a memory cell region of an AND type flash memory according to an embodiment of the present invention in the order of manufacturing steps.

In FIGS. 1 to 14, the cross-sectional views are taken in the direction of the word line corresponding to aa 'of the top view of the pattern (A).
In the pattern top view, the data line direction corresponding to bb 'in the pattern top view is (B), and the data line direction corresponding to c-c' in the pattern top view is (C). The one in the word line direction corresponding to d-d 'is shown as (D). Also, in FIGS. 1 to 14, for easy viewing of the drawings, symbols are attached to main parts formed in the steps of each drawing, and symbols already described are omitted.

A memory gate insulating film 1, a first polycrystalline silicon film 2, and a silicon nitride film 3 are sequentially deposited on a semiconductor substrate, and are patterned as shown in the pattern top view of FIG. FIG. 1 shows the silicon nitride film 3 on the outermost surface of the pattern.

The pattern of FIG. 1 is divided into a memory area, a remaining gate area, a selection MOS area, and a CONT area from the left of FIG. In the memory area, a storage MO which is a memory cell is provided.
An SFET is formed. A remaining gate is formed in the remaining gate region, and the remaining gate is connected to the control gate electrode of the memory cell formed in the memory region and the selection MO as described later.
Since the gate electrode of the select MOSFET formed in the S region is formed of the same thin film, the gate electrode is provided for buffering the gate electrode during etching. In the selection MOS region, a sub-bit line of a memory block, which is a group of storage MOSFETs formed in the memory region, is connected to one of the source / drain regions, and a selection MOSFET for selecting the sub-bit line is formed. The CONT region is a region where a connection hole for connecting a metal bit line connected to the other source / drain region of the selection MOSFET is opened.

The thickness of the memory gate insulating film 1 is 7 to
It is formed as thin as 10 nm so that a tunnel current flows. The silicon nitride film 3 and the underlying first polycrystalline silicon film 2 are patterned so as to form the drain and source of the storage MOSFET.

As shown in the sectional view (A1) of FIG. 2, a memory gate insulating film 1, a first polycrystalline silicon film 2 and a silicon nitride film 3 are sequentially deposited on a semiconductor substrate, Storage MOSFE with pattern as shown in the figure
An opening is formed in a region serving as a drain and a source of T. further,
After the light oxide film 4 is formed, the drain and source portions are separately opened by using a resist film, and a diffusion layer forming the common drain 5 and source 6 of the storage MOSFET is formed by ion implantation and annealing. At this time, the drain and source diffusion layers of adjacent memory cell blocks are common.

The memory gate insulating film 1 is made of a first polycrystalline silicon film 2 and a silicon nitride film 3 by thermal oxidation.
Can be formed by a CVD method. In addition, a known dry etching method can be used for the opening of the region serving as the drain and the source.

The reason why the drain and source portions are formed using different resist films is to make the impurity concentrations of the drain and the source different. This allows
It is possible to optimize the impurity concentration while maintaining a balance between an impurity concentration sufficient to allow a tunnel current to flow and an impurity concentration sufficient to prevent punch-through.

As shown in the sectional view (A2) of FIG.
After the formation of the silicon nitride film by the method D, sidewalls 7 are formed on the side surfaces of the first-layer polycrystalline silicon film 2 by overall etch back.

As shown in the sectional view (A3) of FIG. 2, a selective oxide film 8 is selectively formed on the drain and the source doped with As by thermal oxidation. At this time, the sidewall 7 serves as a stopper so that the end of the first-layer polycrystalline silicon film 2 is not oxidized, and no bird's beak is formed below the end of the first-layer polycrystalline silicon film 2. Thereby, the thickness of the memory gate insulating film 1 becomes the first
It is uniform over the entire area of the layer polycrystalline silicon film 2, and the performance of the memory cell can be improved.

In the steps of the cross-sectional views (A1) to (A3) of FIG.
As shown in the sectional views (A1) to (A3) of FIG.
Although the first polycrystalline silicon film 2 serving as the lower floating gate electrode is separated, the memory M of the same memory cell block is not separated.
The OSFET remains integrally formed as shown in the cross-sectional view (B) of FIG. Further, as shown in the cross-sectional view (C) of FIG. 2, in the select MOS region and the CONT region, the first-layer polycrystalline silicon film 2 as the lower floating gate electrode is still integrally formed.

Next, as shown in the pattern top view of FIG. 3 and the sectional views (A1), (B), and (C) of FIG. 4, the semiconductor substrate is immersed in hot phosphoric acid to form the silicon nitride film 3 and The sidewall 7 is completely removed. Thereby, the first-layer polycrystalline silicon film 2 (lower floating gate electrode)
And the selective oxide film 8 remains.

As shown in the sectional view (A2) of FIG.
A PAD oxide film 9 and a second-layer polycrystalline silicon sidewall 10 are formed at the end of the first-layer polycrystalline silicon film 2 by etching back the entire surface after forming the silicon oxide film and the second-layer polycrystalline silicon film by the method D. I do.

By using polycrystalline silicon, which is a material different from the underlying silicon oxide, as the second-layer polycrystalline silicon sidewall 10, it is possible to perform etch-back under etching conditions that provide an etching selectivity. In addition, a processing margin can be provided for the etch back at the time of forming the sidewall.

As shown in the pattern top view of FIG.
A layer polycrystalline silicon film 11 and a trench isolation (element isolation region having a trench structure) are formed. This third-layer polycrystalline silicon film 11 constitutes an upper floating gate electrode, and is removed by etching on the selective oxide film 8 to separate the floating gate electrode between memory cell blocks. Further, the selective oxide film 8, the drain 5, the source 6, and the semiconductor substrate are removed by etching with the same pattern as that of the third-layer polycrystalline silicon film 11, so that trench isolation between memory cell blocks is formed. That is, the third layer polycrystalline silicon film 11 and the trench isolation can be formed using the same mask, and the number of masks can be reduced by one compared with the conventional process.

As shown in the sectional view (A1) of FIG. 6, the floating gate electrode of the storage MOSFET is composed of the first polycrystalline silicon film (lower floating gate electrode) 2 and the second polycrystalline silicon film (floating gate). A gate electrode side wall 10 and a third-layer polycrystalline silicon film 11 formed thereon are formed in a T-shape covering the drain 5 and the source 6.

As shown in the cross-sectional view (C1) of FIG. 6, in the select MOS region, the first-layer polycrystalline silicon film 2 and the third-layer polycrystalline silicon film 11 are removed by etching in the pattern shown in FIG. Further, the substrate is etched away in the same pattern.

As shown in the sectional views (A2) and (C2) of FIG. 6, light oxidation 12 is formed on the side wall and the bottom of the trench isolation.

As shown in the cross-sectional views (A3) and (C3) of FIG. 6, a trench isolation buried portion 13 is formed by etching back the entire surface after forming a silicon oxide film by the CVD method.

In the steps of the cross-sectional views (A1) to (A3) of FIG.
The FET has a floating gate electrode separated as shown in the figure, but the storage MOSFET of the memory cell block has
As shown in the cross-sectional view (B) of FIG. 6, it is still formed integrally. Further, as shown in the cross-sectional views (A1) to (A3) of FIG. 6, the drain and source diffusion layers of adjacent memory cell blocks are separated by trench isolation. Also, as shown in the sectional views (C1) to (C3) of FIG.
By the trench isolation, the selection MOS regions of the adjacent memory cell blocks are separated.

Next, as shown in the top view of the pattern in FIG. 7, the portion where the selection MOS is formed is removed by etching substantially at the center of the portion where the interlayer insulating film 14 is formed and becomes a remaining gate later. You.

That is, the sectional views (A), (B1),
As shown in (C1), the third-layer polycrystalline silicon film 1
An interlayer insulating film 14 is formed on 1. The above interlayer insulating film 1
4 is SiO ₂ / Si ₃ N ₄ / SiO ₂ / Si ₃ from below
Four layers of N ₄ are formed by the CVD method.

As shown in the cross-sectional views (B2) and (C2) of FIG. 8, the interlayer of the portion where the selection MOS is formed so as to cover the memory portion around substantially the center of the portion to be the remaining gate later. The insulating film 14, the first polycrystalline silicon film (lower floating gate electrode) 2, and the third polycrystalline silicon film (upper floating gate electrode) 11 are etched away. Thereafter, a sacrificial oxide film is formed, and after removal, a gate insulating film 15 of the select MOS and the peripheral MOS is formed. At this time, since the uppermost Si ₃ N ₄ of the interlayer insulating film 14 functions as a mask, the above-described oxidation and removal are not performed in the memory portion.

As shown in the pattern top view of FIG.
A layer polycide film 16 is formed. That is, the fourth layer polycide film 16 is formed of polysilicon / WS in order from the bottom.
It is made of silicide / CVD-SiO ₂ such as i ₂ and MoSi ₂ .

As shown in the sectional views (A), (B), and (C) of FIG. 10, the fourth layer polycide film 16 includes a word line, a select MOS, a remaining gate, and a peripheral MOS portion (not shown). It is removed by etching while remaining.

As shown in the pattern top view of FIG. 11 and the sectional views (A), (B) and (C) of FIG. 12, the selection MOS section and the peripheral MOS section except for the memory section are bordered by the remaining gate. covered with a resist film or the like, the self-alignment of the memory end of the memory portion and the remaining gate is a CVD-SiO ₂ of the fourth layer polycide film 16 as a mask, the interlayer insulating film 1
4, the first-layer polycrystalline silicon film 2, the second-layer polycrystalline silicon sidewall 10, and the third-layer polycrystalline silicon film 11 are removed by etching.

As shown in the pattern top view of FIG. 13 and the sectional views (B1) and (D1) of FIG. 14, the memory portion is covered with a resist film or the like, and the fourth layer polycide is formed in the select MOS region and the peripheral MOS region. CVD-SiO of film 16
Source and source by self-alignment using ₂ as a mask
Opening of the drain is performed to form a source / drain diffusion layer 17. At this time, as shown in the sectional view (D1) of FIG. 14, the diffusion layer wiring end of the memory section and the diffusion layer of the selection MOSFET are formed so as to overlap. Further, sidewalls 18 are formed on the gate electrodes of the MOSFETs in the selection MOS region and the peripheral MOS region.

Further, the sectional views (A), (B2),
As shown in (C) and (D2), an insulating film 19 is formed on the entire surface of the semiconductor substrate, and a connection hole is opened in the CONT region.

The formation of the metal wiring after the opening of the connection hole can be performed by a known sputtering method or the like, and the description is omitted.

According to the manufacturing method of the present embodiment, the following effects can be obtained.

(1) The oxidized region of the selective oxide film 8 formed above the drain 5 and the source 6 of the storage MOSFET is replaced with the first polycrystalline silicon film 2 serving as a lower floating gate electrode.
Since the thickness of the selective oxide film 8 can be determined without variation, the storage MOS
Variations in FET characteristics are reduced, and a processing margin can be easily secured.

(2) Since the isolation of the storage MOSFET can be formed simultaneously with the mask process for processing the third polycrystalline silicon film 11 serving as the upper floating gate electrode, the mask process can be reduced.

(3) By forming the second-layer polycrystalline silicon sidewall 10 of the storage MOSFET with polysilicon, the margin of the sidewall process can be expanded.

As described above, the AND type flash memory manufactured by the manufacturing method of this embodiment has an element isolation structure by trench isolation. According to such an AND flash memory, since it has an element isolation structure by trench isolation, it is not necessary to form a field insulating film made of a LOCOS oxide film, and the reliability of the memory cell can be improved.

In the above embodiment, the thickness of the memory gate insulating film 1 is set to 13 nm or more, and the thickness of the PAD oxide film 9 of the second-layer polycrystalline silicon sidewall 10 is formed to about 7 to 10 nm. It is also possible to rewrite the memory through the PAD oxide film 9. In such a case, since a tunnel current can flow through the PAD oxide film 9, information can be reliably rewritten, and
The margin for punch-through can be increased by minimizing the impurity concentration of the drain 5 or the source 6 to a necessary minimum.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the present embodiment, a polycrystalline silicon or silicide film is used as a gate wiring material, and a silicon oxide film or the like is used as a material for an interlayer insulating film therebetween and a material for a buried insulating film for trench isolation. It is not limited to such materials,
Any material can be employed as long as the material ensures conductivity or insulation. Further, as the forming method, known film forming methods and etching methods can be used alone or in combination.

[0077]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) The number of masks for processing in the direction parallel to the sub-bit lines in the memory cell block can be reduced, and the manufacturing process of the semiconductor integrated circuit device can be simplified.

(2) The thickness of the selective oxide film formed on the buried diffusion layer wiring can be made uniform, the device characteristics of the memory cell can be stabilized, and high integration can be achieved.

(3) It is possible to avoid deterioration of device characteristics due to a decrease in an etch margin with respect to a selective oxide film when forming a silicon oxide film sidewall.

(4) A margin for punch-through or short-circuit between channels can be secured, and the information writing operation can be performed reliably.

[Brief description of the drawings]

FIG. 1 is a pattern top view showing a memory cell region of an AND flash memory according to an embodiment of the present invention in a manufacturing process order.

FIG. 2 is a sectional view corresponding to aa ′, bb ′, and cc ′ of FIG. 1;

FIG. 3 is a pattern top view showing a memory cell region of an AND flash memory according to an embodiment of the present invention in the order of manufacturing steps;

FIG. 4 is a sectional view corresponding to aa ′, bb ′, and cc ′ in FIG. 3;

FIG. 5 is a pattern top view showing a memory cell region of an AND flash memory according to an embodiment of the present invention in the order of manufacturing steps;

FIG. 6 is a sectional view corresponding to aa ′, bb ′, and cc ′ of FIG. 5;

FIG. 7 is a pattern top view showing a memory cell region of an AND flash memory according to an embodiment of the present invention in a manufacturing process order;

FIG. 8 is a sectional view corresponding to aa ′, bb ′, and cc ′ in FIG. 7;

FIG. 9 is a pattern top view showing a memory cell region of an AND flash memory according to an embodiment of the present invention in the order of manufacturing steps;

FIG. 10 is a sectional view corresponding to aa ′, bb ′, and cc ′ in FIG. 9;

FIG. 11 is a pattern top view showing a memory cell region of an AND flash memory according to an embodiment of the present invention in a manufacturing process order;

FIG. 12 is a sectional view corresponding to aa ′, bb ′, and cc ′ of FIG. 11;

FIG. 13 is a pattern top view showing a memory cell region of an AND flash memory according to an embodiment of the present invention in a manufacturing process order;

14 is aa ′, bb ′, cc ′, and d in FIG.
It is sectional drawing corresponding to -d '.

[Explanation of symbols]

 Reference Signs List 1 memory gate insulating film 2 first layer polycrystalline silicon film 3 silicon nitride film 4 light oxide film 5 drain 6 source 7 side wall 8 selective oxide film 9 PAD oxide film 10 second layer polycrystalline silicon sidewall 11 third layer poly Crystal silicon film 12 Light oxidation 13 Buried portion 14 Interlayer insulating film 15 Gate insulating film 16 Fourth layer polycide film 17 Drain diffusion layer 18 Side wall 19 Insulating film

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H01L 27/10 481

Claims (6)

[Claims] A floating gate electrode having a lower floating gate electrode and an upper floating gate electrode formed on a main surface of a semiconductor substrate via a first gate insulating film; and a floating gate electrode formed on a side of the lower floating gate electrode. A selective oxide layer formed below the upper floating gate electrode, and a channel region formed on a main surface of the semiconductor substrate below the first gate insulating film, the lower portion of the selective oxide layer And a MISFE formed in a part of a lower portion of the first gate insulating film.
A nonvolatile memory cell including an impurity semiconductor region functioning as a source or a drain of T and a control gate electrode formed above the upper floating gate electrode with an interlayer insulating film interposed therebetween; Cells are connected in parallel by the impurity semiconductor regions shared by each other to form an AND-type nonvolatile memory cell block, and the control gate electrode extends to a plurality of nonvolatile memory cell blocks, and A semiconductor integrated circuit device shared by non-volatile memory cells in different non-volatile memory cell blocks, wherein the non-volatile memory cell block has an element isolation structure composed of a buried silicon oxide film embedded in a trench structure. A semiconductor integrated circuit device which is electrically insulated. 2. The semiconductor integrated circuit device according to claim 1, wherein the floating gate electrode is formed between the lower floating gate electrode, the upper floating gate electrode, and the lower floating gate electrode and the selective oxidation layer. Wherein the first sidewall is made of polycrystalline silicon formed on a main surface of the semiconductor substrate with a second gate insulating film interposed therebetween. apparatus. 3. The semiconductor integrated circuit device according to claim 2, wherein the operation of recording information in said nonvolatile memory cell is performed by a tunnel current passing through said second gate insulating film. A semiconductor integrated circuit device characterized by the above-mentioned. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein after forming a selective oxide film on said impurity semiconductor region,
A method for manufacturing a semiconductor integrated circuit device, comprising forming a trench structure in a central portion of the selective oxide film and the impurity semiconductor region to form the element isolation structure. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein an edge of the upper floating gate electrode in a direction parallel to the impurity semiconductor region is formed in the same step as the processing of the trench structure. A method of manufacturing a semiconductor integrated circuit device, characterized by processing. 6. The method for manufacturing a semiconductor integrated circuit device according to claim 4, wherein a peripheral circuit region other than a memory cell region in which said nonvolatile memory cell is arranged is simultaneously formed with said element isolation structure. A method for manufacturing a semiconductor integrated circuit device, comprising forming an element isolation structure.