KR100255159B1 - Method of fabricating source-line-segment transistor in flash eeprom cell array - Google Patents

Abstract

PURPOSE: A method for manufacturing a source line segment transistor is provided to improve an electrical characteristic of devices by reducing the size of a segment transistor by forming a junction of a source line segment transistor in a self-alignment. CONSTITUTION: A method for manufacturing a source line segment transistor forms the first and second drain junctions(203a,203b) at a semiconductor substrate(201) in a source line segment transistor region by means of the first ion implantation process. Thermal oxide films(204) are formed on the first and second drain junctions(203a,203b), respectively. A gate oxide film(205) is formed on the semiconductor substrate(201) between the first and second drain junctions(203a,203b). The first gate electrode(206a) a portion of which overlaps with the second drain junction(203b) is formed on the gate oxide film(205). A self-aligned source junction(203c) is formed in the semiconductor substrate(201) between the first and second gate electrodes(206a,206b) by means of the second ion implantation process and two source line segment transistors are formed. An interlayer dielectric(209) is formed on the entire surface including the two source line segment transistors. A contact hole(210) for connecting a metal wire is formed in the source junction.

Description

Source Line Segment Transistor Manufacturing Method of Flash Ipyrom Cell Array

The present invention relates to a method for manufacturing a source line segment transistor of a flash EEPROM cell array, and in particular, to make the junction of the source line segment transistor be self-aligned. The present invention relates to a method of manufacturing a source line segment transistor capable of improving the electrical characteristics and reducing the size of the segment transistor.

In general, a contactless NOR type split gate type flash EEPROM cell array comprises a source line segment transistor and a peripheral circuit transistor. The source line segment transistor is a transistor used to increase the operating speed by reducing the capacitance of the source line of the cell array region operating by blocking an inoperable cell array region during a read operation in a flash Y pyrom cell array. .

A conventional method of manufacturing a source line segment transistor will be described with reference to FIGS. 2 (a) to 2 (d), which are cross-sectional views taken along the layout diagram of FIG. 1 and the line A-A 'of FIG.

Referring to FIGS. 1 and 2 (a), an ion implantation process using a photoresist pattern 102 having a source / drain junction region open on a semiconductor substrate 101 of a source line segment transistor region 130 as a mask is performed. First and second drain junctions 103a and 103c and source junction 103b are formed.

In the above, the photoresist pattern 102 is formed with first and second drain junctions 103a and 103c and a source junction 103b.

In the above, the photoresist layer pattern 102 sequentially forms the field oxide film, the tunnel oxide film, the polysilicon film for the floating gate, the dielectric film, the polysilicon film for the control gate and the oxide film in the first and second cell array regions 120 and 140. After the floating gate and the control gate are formed by self-aligned etching, they are simultaneously formed during a lithography process using a cell source / drain mask. The first and second drain junctions 103a and 103c and the source junction 103b are simultaneously formed during the cell source / drain ion implantation process. The first drain junction 103a is commonly used with the drain junction of the first cell array region 120, and the second drain junction 103c is commonly used with the drain junction of the second cell array region 140.

Referring to FIGS. 1 and 2 (b), after removing the photoresist pattern 102, a thermal oxide film 104 is formed on each of the first and second drain junctions 103a and 103c and the source junction 103b. The gate oxide film 105 is formed on the semiconductor substrate 101 between the first and second drain junction portions 103a and 103c and the source junction portion 103b.

In the above, the thermal oxide film 104 is formed simultaneously in the poly oxidation process performed after the cell source / drain ion implantation in the cell array regions 120 and 140.

The gate oxide film 105 is formed at the same time in the gate oxide film formation process of the peripheral circuit transistor which is performed after the threshold voltage control ion implantation process of the peripheral circuit transistor.

Referring to FIGS. 1 and 2C, a first gate electrode 106a is formed on the gate oxide film 105 between the first drain junction 103a and the source junction 103b, and the source junction portion ( The second gate electrode 106b is formed on the gate oxide film 105 between the 103b and the second drain junction 103c. Each of the first and second gate electrodes 106a and 106b is formed to sufficiently overlap the thermal oxide film 104. Through the above steps, two source line segment transistors having the source junction 103b in common form.

In the above, the first and second gate electrodes 106a and 106b are simultaneously formed in the select gate formation process using the select gate masks implemented in the first and second cell array regions 120 and 140. The select gate is widely used as a polysilicide structure in which a polysilicon layer and a metal silicide layer are stacked. The first and second gate electrodes 106a and 106b are also formed as a polyside structure because they are formed in the same process as the select gate. .

Referring to FIGS. 1 and 2 (d), after forming the interlayer insulating film 107 over the entire structure including two source line segment transistors, the source junctions of the first and second gate electrodes 106a and 106b ( A contact hole 108 is formed in 103b for connecting the metal wires.

In FIG. 1, reference numeral 109 denotes an isolation layer that defines an active region and a field region.

When the source line segment transistor is manufactured by the above method, the following problem occurs. As the source line segment transistor exists in the cell array, the gate of the source line segment transistor is determined to be a select gate mask that is the same layer as the word line (select gate), thereby increasing the overall size of the cell array by the size of the source line segment transistor. Therefore, as the degree of integration of semiconductor devices increases, it is necessary to reduce the size of the source line segment transistor in order to reduce the overall size of the cell array. However, since the source line segment transistor manufacturing method uses a method of forming a gate after forming a junction, the gate must be properly aligned at the junction in order to completely overlap the gate in the channel region. In order to properly align the gate to the junction, each process, for example, an alignment process such as a self alignment mask process, a cell source / drain mask process, a select gate mask process, and the like must be precisely performed. However, in the course of these processes, misalignment occurs, so that the gate is sufficiently overlapped with the junction in consideration of the degree of misalignment, and the gate length becomes excessively large, thereby increasing the size of the source line segment transistor. In addition, since the cell source / drain ion implantation requires several thermal processes, the lateral diffusion of the junction increases, thereby reducing the effective channel length. is more likely to occur.

Accordingly, the present invention allows the junction of the source line segment transistor to be formed by self alignment, thereby reducing the size of the segment transistor and improving electrical characteristics, and reducing the overall size of the cell array so as to achieve high integration of the device. It is an object of the present invention to provide a method for manufacturing a segment transistor.

According to an aspect of the present invention, there is provided a method of forming a first and second drain junctions on a semiconductor substrate in a source line segment transistor region by a first ion implantation process, and a column on each of the first and second drain junctions. Forming an oxide film, forming a gate oxide film on the semiconductor substrate between the first and second drain junctions, partially overlapping the first drain junction, and forming a first gate electrode on the gate oxide film, Forming a second gate electrode on the gate oxide layer and partially overlapping the second drain junction, and forming a self-aligned source junction on the semiconductor substrate between the first and second gate electrodes by a second ion implantation process. Four source line segment transistors are formed, and all of the two source line segment transistors are After the interlayer insulating film is formed on the upper portion, forming a contact hole for connecting the metal wiring to the source junction.

1 is a layout diagram of a conventional source line segment transistor.

2 (a) to 2 (d) are cross-sectional views of elements for explaining a conventional method for manufacturing a source line segment transistor.

3 is a layout diagram of a source line segment transistor according to the first embodiment of the present invention.

4 (a) to 4 (e) are cross-sectional views of devices for explaining the method for manufacturing a source line segment transistor according to the first embodiment of the present invention.

5 is a layout diagram of a source line segment transistor according to a second embodiment of the present invention.

6 (a) to 6 (e) are cross-sectional views of a device for explaining a method of manufacturing a source line segment transistor according to a second embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

101, 201, 301: semiconductor substrate 102: photosensitive film pattern

103a, 203a: first drain junction 103b, 203c, 303c: source junction

103c, 203b: second drain junction

303a: drain junction of the first cell array

303b: drain junction of the second cell array

303d: drain junction of the first segment transistor

303e: drain junction of the second segment transistor

104, 204, 304: thermal oxide film 105, 205, 305: gate oxide film

106a, 206a, 306a: first gate electrode

106b, 206b, 306b: second gate electrode

107, 209, 309: interlayer insulating film 202, 302: first photosensitive film pattern

208 and 308: second photosensitive film pattern 108, 210 and 310: contact hole

207, 307: spacer 109, 211, 311: device isolation film

120, 220, 320: 1st cell array area

130, 230, 330: source line segment transistor region

140, 240, 340: second cell array region

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

A method of manufacturing a source line segment transistor according to a first embodiment of the present invention will be described with reference to FIGS. 4 (a) to 4 (e), which are cross-sectional views taken along the BB ′ line of FIG. Is as follows.

Referring to FIGS. 3 and 4 (a), the first photoresist film pattern 202 having the first and second drain junction regions open to the semiconductor substrate 201 of the source line segment transistor region 230 as a mask is used as a mask. First and second drain junctions 203a and 203b are formed by an ion implantation process.

In the above description, the first photoresist layer pattern 202 sequentially forms a field oxide layer, a tunnel oxide layer, a floating silicon polysilicon layer, a dielectric layer, a control gate polysilicon layer, and an oxide layer in the first and second cell array regions 220 and 240. After forming the floating gate and the control gate by a self-aligned etch (etch-self), and formed at the same time in the lithography process using a cell source / drain mask. The first and second drain junctions 203a and 203b are simultaneously formed during the cell source / drain ion implantation process. The first drain junction 203a is commonly used with the drain junction of the first cell array region 220, and the second drain junction 203b is commonly used with the drain junction of the second cell array region 240.

Referring to FIGS. 3 and 4 (b), after removing the first photoresist pattern 202, a thermal oxide film 204 is formed on each of the first and second drain junctions 203a and 203b, and the first And a gate oxide film 205 is formed on the semiconductor substrate 201 between the two drain junction portions 203a and 203b.

In the above, the thermal oxide film 204 is formed at the same time in the poly oxidation process performed after the cell source / drain ion implantation in the cell array regions 220 and 240, and the thickness thereof is about 300 to 700 kPa. The gate oxide film 205 is simultaneously formed during the gate oxide film formation process of the peripheral circuit transistor which is performed after the threshold voltage control ion implantation process of the peripheral circuit transistor.

Referring to FIGS. 3 and 4 (c), a first gate electrode 206a is formed on the gate oxide film 205 between the first drain junction 203a and the region where the source junction is to be formed, and the source junction The second gate electrode 206b is formed on the gate oxide film 205 between the region where the is to be formed and the second drain junction 203b. One side of the first gate electrode 206a overlaps the thermal oxide film 204 formed on the first drain junction 203a, and one side of the second gate electrode 206b is a column formed on the second drain junction 203b. It is formed to overlap the oxide film 204.

In the above, the first and second gate electrodes 206a and 206b are simultaneously formed in the select gate forming process using the select gate mask implemented in the first and second cell array regions 220 and 240. The select gate is widely used as a polysilicide structure in which a polysilicon layer and a metal silicide layer are stacked. Since the first and second gate electrodes 206a and 206b are formed in the same process as the select gate, the select gate is also formed as a polyside structure. .

Referring to FIGS. 3 and 4 (d), thermal oxide films including sidewalls of the first and second gate electrode sidewalls forming spacers 207 and portions of the first and second gate electrodes 206a and 206b, respectively, After forming the second photoresist layer pattern 208 on the upper portion of the electrode 204, an ion implantation process is performed to align the source junction portion 203c with the semiconductor substrate 201 between the first and second gate electrodes 206a and 206b. Is formed. Through the above steps, two source line segment transistors having the source junction portion 203c in common have a shape.

In the above, the second photoresist layer pattern 208 is simultaneously formed during a lithography process using a source / drain mask of a peripheral circuit transistor. The source junction 203c is formed at the same time during the source / drain ion implantation process of the peripheral circuit transistor.

Referring to FIGS. 3 and 4 (e), after forming an interlayer insulating film 209 on the entire top including two source line segment transistors, a contact hole 210 for connecting a metal wiring to the source junction 203c is described. ) Is formed.

Reference numeral 211 not described in FIG. 3 denotes an isolation layer defining an active region and a field region.

According to the first embodiment of the present invention described above, since the drain junction of the source line segment transistor commonly used with the drain junction of the cell array region is formed by a cell source / drain ion implantation process before forming the gate electrode, The gate electrode to be formed should be formed such that one side of the gate electrode is sufficiently overlapped with the drain junction in consideration of misalignment. However, the source junction of the source line segment transistor is formed on the gate electrode during the source / drain ion implantation process of the peripheral circuit transistor after the gate electrode is formed. The other side of the gate electrode need not overlap with the source junction because it is formed in self alignment with respect to the source junction. Therefore, the length of the gate electrode can be reduced by the overlapping portion of the conventional source junction, so that high integration of the device can be realized, and the source junction of the present invention is formed after several thermal processes such as a poly oxidation process and a gate oxide film formation process. As a result, lateral diffusion is reduced, thereby enhancing the characteristics for punch-drow.

A method of manufacturing a source line segment transistor according to a second embodiment of the present invention will be described with reference to FIGS. 6 (a) to 6 (e), which are cross-sectional views taken along the CC ′ line of FIG. Is as follows.

Referring to FIGS. 5 and 6 (a), the semiconductor substrate 301 of the source line segment transistor region 330 has a first photoresist pattern 302 covering the source line segment transistor region 330 as a mask. Drain junctions 330a and 303b of the first and second cell arrays are formed by an ion implantation process.

In the above description, the first photoresist layer pattern 302 sequentially processes the field oxide layer, the tunnel oxide layer, the floating layer polysilicon layer, the dielectric layer, the control gate polysilicon layer, and the oxide layer in the first and second cell array regions 320 and 340. After forming the floating gate and the control gate by a self-aligned etch (etch alignment), it is formed simultaneously in the lithography process using a cell source / drain mask. The drain junctions 303a and 303b of the first and second cell arrays are formed during the cell source / drain ion implantation process. The drain junction 303a of the first cell array is formed in the first cell array region 320, and the drain junction 303b of the second cell array is formed in the second cell array region 340.

Referring to FIGS. 5 and 6 (b), after the first photoresist layer pattern 302 is removed, a thin thermal oxide layer 304 is formed on the drain junctions 303a and 303b of the first and second cell arrays. A gate oxide film 305 is formed over the semiconductor substrate 301 between the drain junctions 303a and 303b of the first and second cell arrays, which are the source line segment transistor regions 330.

In the above, the thermal oxidation film 304 is thinly formed to a thickness of 300 kPa or less during the poly oxidation process performed in the first and second cell array regions 320 and 340. The gate oxide film 305 is simultaneously formed during the gate oxide film formation process of the peripheral circuit transistor which is performed after the threshold voltage control ion implantation process of the peripheral circuit transistor.

5 and 6 (c), first and second gate electrodes 306a and 306b are formed at selected portions between the drain junctions 303a and 303b of the first and second cell arrays, respectively.

In the above, the first and second gate electrodes 306a and 306b are simultaneously formed in the select gate forming process using the select gate masks implemented in the first and second cell array regions 320 and 340. The select gate is widely used as a polysilicide structure in which a polysilicon layer and a metal silicide layer are stacked. The first and second gate electrodes 306a and 306b are also formed of a polyside structure because they are formed in the same process as the select gate. .

5 and 6 (d), spacers 307 are formed on sidewalls of the first and second gate electrodes 306a and 306b, respectively, and the source line segment transistor region 330 is sufficiently open. By the ion implantation process using the second photoresist pattern 308 as a mask, the drain junction portions 303d and 303e and the source junction portion 303c of the first and two segment transistors are formed on the semiconductor substrate 301 in self-alignment, respectively. . The drain junction 303d of the first segment transistor is connected to the drain junction 303a of the first cell array, and the source junction 303c is formed between the first and second gate electrodes 306a and 306b and the second segment. The drain junction 303e of the transistor is formed to be connected to the drain junction 303b of the second cell array. Through the above steps, two source line segment transistors having the source junction portion 303c in common are formed.

In the above, the second photoresist layer pattern 308 is simultaneously formed during the lithography process using the source / drain mask of the peripheral circuit transistor. The drain junctions 303d and 303e and the source junction 303c of the first and two segment transistors are formed at the same time during the source / drain ion implantation process of the peripheral circuit transistor.

Referring to FIGS. 5 and 6 (e), after forming an interlayer insulating film 309 on the entire top including two source line segment transistors, a contact hole 310 for connecting metal wires to the source junction 303c. ) Is formed.

Reference numeral 311 not described in FIG. 5 denotes an isolation layer defining active regions and field regions.

According to the second embodiment of the present invention, the drain junction portion and the source junction portion of the source line segment transistor are formed in self alignment with the gate electrode during the source / drain ion implantation process of the peripheral circuit transistor after the gate electrode is formed. Both sides need not overlap the drain junction and the source junction. Therefore, the length of the gate electrode can be reduced by overlapping portions of the conventional drain junction and the source junction, so that high integration of the device can be realized, and the drain junction and the source junction of the present invention can be subjected to several thermal processes such as a poly oxidation process and a gate oxide film formation process. Since it is formed after the lateral diffusion, the side diffusion is reduced to enhance the characteristics for the punch-drow.

Meanwhile, the drain junction of the source line segment transistor should be interconnected with the drain junction of the cell array. However, in the second embodiment of the present invention, the source line segment transistor is formed by the source / drain ion implantation process of the peripheral circuit transistor in a state in which the drain junction of the cell array is first formed and the thermal oxide film is formed on the drain junction of the cell array. The drain junction of was made. In general, since the source / drain junction of the peripheral circuit transistor is formed as a shallow junction, when the thickness of the thermal oxide film formed on the drain junction of the cell array is thick, the source / drain ions are blocked by the thermal oxide film. As a result, the drain junction of the source line segment transistor and the drain junction of the cell array are not well connected, which greatly increases the interconnect resistance value, thereby degrading the continuity characteristic. Therefore, in the second embodiment of the present invention, the above problem is solved by forming the thermal oxide film at 300 kPa or less.

As described above, the present invention has the following effects. As the self-aligned junction structure is formed, there is a fear of insufficient overlap between the gate and the junction due to misalignment, so that the length of the gate may not be made excessively larger than the required channel length, thereby reducing the size of the entire cell array. In addition, as the junction is formed after several thermal processes and the junction is formed by self-alignment, it is possible to improve the breakdown voltage, current and punch-draw characteristics and increase uniformity.

Claims (15)

Forming first and second drain junctions in a first ion implantation process on a semiconductor substrate in the source line segment transistor region, and forming a thermal oxide layer on each of the first and second drain junctions, Forming a gate oxide film on a semiconductor substrate between the drain junctions, a portion of the gate oxide layer overlapping the first drain junction, and a first gate electrode formed on the gate oxide layer, and a portion of the second drain junction overlapping the second drain junction; Forming a second gate electrode on the gate oxide film, and forming a self-aligned source junction in a semiconductor ion between the first and second gate electrodes by a second ion implantation process to form two source line segment transistors; Forming an interlayer insulating film on the whole including the two source line segment transistors; Source line segments transistor manufacturing method of this pirom flash cell array, characterized in that comprising the step of forming a contact hole for connecting metal wires to agarose junction. The method of claim 1, wherein the first and second drain junctions are formed during an ion implantation process using a cell source / drain mask. The method of claim 1, wherein each of the first and second drain junctions uses a cell array region in common with a drain junction. The method of claim 1, wherein the thermal oxide layer is formed to have a thickness of about 300 to 700 μm during a poly oxidation process in a cell array region. The method of claim 1, wherein the gate oxide film is formed during a gate oxide film formation process of a peripheral circuit transistor. The method of claim 1, wherein the first and second gate electrodes are formed during a select gate formation process in a cell array region. The method of claim 1, wherein the source junction is formed during an ion implantation process using a source / drain mask of a peripheral circuit transistor. Covering the source line segment transistor region with a photoresist layer and forming a drain junction of the first and second cell arrays in a selected region of the semiconductor substrate by a first ion implantation process, and forming a column on the drain junction of the first and second cell arrays. Forming an oxide film, forming a gate oxide film on a semiconductor substrate in the source line segment transistor region, and forming first and second gate electrodes at selected portions between the drain junctions of the first and second cell arrays, respectively. And forming a source line segment transistor in the selected region on the semiconductor substrate by forming a drain junction and a source junction of the first and second segment transistors in a self-aligned manner in a second ion implantation process, and forming the two source line segment transistors. An interlayer insulating film is formed over the whole including the segment transistor And forming a contact hole for connecting a metal line to the source junction after the source line segment transistor of the flash Y pyrom cell array. 10. The method of claim 8, wherein the drain junctions of the first and second cell arrays are formed during an ion implantation process using a cell source / drain mask. 10. The method of claim 8, wherein the thermal oxide film is formed to a thickness of about 300 microseconds during a poly oxidation process in a cell array region. 10. The method of claim 8, wherein the gate oxide film is formed during a gate oxide film formation process of a peripheral circuit transistor. The method of claim 8, wherein the first and second gate electrodes are formed during a select gate forming process in a cell array region. The drain junction of the first segment transistor is connected to the drain junction of the first cell array, wherein the source junction is formed between the first and second gate electrodes, and the drain junction of the second segment transistor. A source line segment transistor manufacturing method of a flash y-pyrom cell array, characterized in that it is connected to the drain junction of the second cell array. The source line segment of the flash Y pyrom cell array of claim 8, wherein the photoresist pattern formed to perform the second ion implantation process is simultaneously formed during a lithography process using a source / drain mask of a peripheral circuit transistor. Transistor manufacturing method. The method of claim 8, wherein the drain junction and the source junction of the first and two segment transistors are simultaneously formed during a source / drain ion implantation process of a peripheral circuit transistor. .

Images