JPH02359A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enable a microcomputer and a non-volatile memory to be formed on the same chip, by forming a non-volatile memory MNOS element simultaneously in the Si gate process producing the microcomputer. CONSTITUTION:A CMOS transistor T1 for constituting a microcomputer and an MNOS transistor T2 for constituting a non-volatile memory element are provided on the same substrate. Active regions 11 constituting the MNOS transistor T2 are formed simultaneously when active regions of the CMOS T1 are formed. An oxide film 6 and a nitride film 5 are also formed during the formation of the active regions. After the formation of the nitride film 5, an aluminium interconnection 7 is provided on the CMOS T1 while, simultaneously, an aluminum interconnection 7 is also formed on the oxide film 6 so that it serves as a gate electrode of the MNOS T2.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method of manufacturing a semiconductor integrated circuit device in which a circuit including a nonvolatile memory and a circuit constituting a microcomputer are provided on the same substrate.

Currently, MN OS is a rewritable non-volatile memory.
(Metal-Nitride-Oxide-8em
(iconductor) type is used. This memory stores stored information by applying high voltages of 10 and - to the gate electrode to accumulate and release charges at the boundary between the nitride film and the oxide film through a thin oxide film. It is. The main MIS elements constituting this memory usually use kl as a gate electrode.
The nitride film as the gate insulating film is approximately 5
00A, the thin oxide film uses approximately 20A, and the process is similar to a normal Al gate type MOS process.

On the other hand, the development of control semiconductor devices has been remarkable, and today microcomputers are made up of one chip (or several chips).
SI has been manufactured (・).These LSIs have become extremely highly integrated and have improved performance (・).For this reason, the Si gate process is usually used as the manufacturing process. High performance S rather than thinking about performance
It is thought that it will be an i-gate process.

On the other hand, when considering the application aspect of microcombinators, nonvolatile memory is becoming necessary as a peripheral IC.Currently, microcombinators and nonvolatile memory are manufactured as separate LSIs and ICs. However, considering future performance improvements, it is desirable to form them on the same chip in terms of integration, cost, performance, etc.

However, as mentioned above, each process is completely different, and so far it has not been realized (・na(
・.

As a method for realizing this, it is considered that the circuit element and the nonvolatile memory element can be relatively easily formed on the same chip by using an Al gate process similar to that used for making the MNO8 element. However, in this method, the circuit elements are formed with an Al gate structure, which is inferior in terms of integration and speed compared to the Si gate process used in current microcomputers. With Vita! 5 I can no longer do things.

On the other hand, considering that it is possible to simultaneously manufacture 8 non-volatile memory MNO elements using the S1 gate process when making a micro combinator, the heat treatment of the Si gate process
It has drawbacks such as the retention characteristics of nonvolatile memory elements deteriorating and the process becoming extremely complicated, so it has not yet been realized (・na(・).

For the reasons mentioned above, non-volatile memory and microcomputers are currently manufactured separately.

The present invention shows a manufacturing method that can easily form this on the same chip and can be realized without losing the drawbacks of both.

According to the present invention, a nonvolatile memory can be easily formed on a high-integration, high-speed, high-performance chip formed by a Si gate process without degrading performance.
As a result, although conventionally the system had to be formed using separate chips, according to the present invention it can be formed using a single chip. On the other hand, by adding non-volatile memory to a microcomputer, the process of microcomputer chips hardly becomes complicated or the price increases.

The present invention will be described below with reference to embodiments shown in the accompanying drawings.

In the following, an example will be shown in which an N-channel MN OS is formed on a C-Mo8Si gate process, but it does not have to be C"Mo8 (N-channel or P-channel is also acceptable. The same applies to a Mo gate or a W gate instead of a Si gate. Also, of course, the same applies to a P-channel as an MNOS.

FIG. 1 shows c-M produced by the manufacturing method of the present invention.

AI in SSi gate! An example is shown in which gate MNOS is formed on the same substrate. N by Si gate process
-channel, P-channel elements are formed. This is exactly the same as a normal Si gate. On the other hand, the nonvolatile memory IJMNO8 uses Al wiring in a Si gate structure as a gate electrode. Therefore, an extra gate electrode layer for forming the MNO8 structure is unnecessary.

Furthermore, the nitride film used in the MNO8 structure is
It is possible to extend it to the top of the VD film, thereby simultaneously improving passivation characteristics.

From the above, the high speed achieved by the Si gate structure.

A highly integrated, high-performance circuit element, an MNO8 element with good characteristics due to the Al gate structure, and good passivation characteristics due to the nitride film can be obtained.

Next, an example of the manufacturing method of the present invention will be shown.

Figure 2 shows a part of the process of the Si GEG CMOS process, and shows a state in which impurities are selectively doped using a mask 10 (by diffusion or implantation). Here, impurities are selectively doped. By using the mask 10, the source and drain of the MNO8 element are doped with impurities,
Separate the area that will become the channel area.

Next, a CVD film, for example, is formed as the interlayer insulating film 12, and a contact hole 13 is formed in a normal Si gate process. At this time, contact holes to the sources and drains of the MNO8 elements and the MNO
Holes are made in the portions that will become the gate regions 14 of the eight elements (FIG. 3).

Next, an oxide film 15 is formed on the contact hole by thermal oxidation or CVD, and MN is formed by photoetching.
The Si substrate is exposed only in the region 16 including the channel region of the O3 element. If the oxide film 15 formed at this time is left in the channel region, an insulated gate transistor equivalent to a device made by a normal Al gate process can be formed through the steps described below. Moreover, this element is actually used as the switch MO3 required in the MNOS type non-volatile memory (this figure is not particularly shown in this example (). Therefore, the oxide film 15
Approximately 500A is appropriate (Fig. 4).

Next, the area that will become the gate of the MNO8 element is extremely thin.
(20-100A) An oxide film 20 is formed, and a nitride film 21 is formed on the entire surface thereof.

At this time, in order to improve the characteristics of the MNO8 element, a step such as forming an impurity layer at the interface between the thin oxide film and the nitride film may be included.

Further, in order to form a contact hole 22, the nitride film and oxide film at the contact portion are removed by photoetching (FIG. 5).

Next, Alt is deposited and patterned to form the gate electrode 7 of the MIS element constituting the nonvolatile memory and the wiring layer 7 of the Si gage MIS element other than the nonvolatile memory, resulting in the structure shown in FIG. something is completed.

Although an example of the manufacturing method has been shown above, it can be realized by various other methods. For example, the contact hole and the MNOS gate region may be formed in separate photoetching steps (i.e., the gate region is first photoetched, a thin oxide layer is formed, the nitride layer is formed, and then the contact portion is formed). It may also be a method of forming.

Alternatively, in order to form the channel region of the MNOS, it is also possible to directly etching the thick oxide film in the field area without using a mask for selective doping with impurities (.

In any case, in the device according to the present invention in the embodiment described above, after forming a circuit element pattern using a Si gate process, a thin oxide film and a nitride film are formed in the MNOS section. The purpose is to use the electrode as the gate electrode of the MNO8 element.

[Brief explanation of the drawing]

Figures 1 and 5 are cross-sectional views showing the insulated gate type medium conductor device and its manufacturing method according to the present invention in the order of steps. 1... Oxide film, 2... Gate oxide film, 3...・・Polycrystalline silicon film for gate electrode, 4・−・Interlayer insulating film, 5・・
・Nitride film, 6... Thin (・Oxide film, 7... Aluminum wiring (electrode), 10... Mask film, 11.
... N medium layer, 12 ... PSG film, 21 ... nitride film.

Claims (1)

[Claims] 1. A method for manufacturing a semiconductor integrated circuit device in which a first circuit including an MIS element constituting a nonvolatile memory and a second circuit including an MIS element other than the MIS element are formed on the same semiconductor substrate. wherein a wiring layer of the MIS element of the second circuit is formed in the same process as a gate electrode forming step of the MIS element that constitutes the nonvolatile memory of the first circuit, and the MIS element that constitutes the nonvolatile memory A method of manufacturing a semiconductor integrated circuit device, characterized in that the wiring layer of the MIS element of the second circuit is formed of the same material as the gate electrode of the semiconductor integrated circuit device. 2. The method according to claim 1, further comprising the step of forming a gate electrode of the MIS element constituting the nonvolatile memory after introducing impurities for forming source and drain regions of the MIS element constituting the nonvolatile memory. A method for manufacturing a semiconductor integrated circuit device. 3. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the MIS element constituting the nonvolatile memory is formed to have a thin gate insulating film on the source and drain regions. .