JPS6397235U - - Google Patents
Info
- Publication number
- JPS6397235U JPS6397235U JP1986193175U JP19317586U JPS6397235U JP S6397235 U JPS6397235 U JP S6397235U JP 1986193175 U JP1986193175 U JP 1986193175U JP 19317586 U JP19317586 U JP 19317586U JP S6397235 U JPS6397235 U JP S6397235U
- Authority
- JP
- Japan
- Prior art keywords
- tape
- metal foil
- holes
- hole
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 8
- 239000011888 foil Substances 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 238000007747 plating Methods 0.000 claims description 4
- 239000008188 pellet Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 claims 1
- 230000002093 peripheral effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Wire Bonding (AREA)
Description
第１図及び第２図は本考案に係る半導体中間構
体の一実施例を示すメツキ処理前及びメツキ処理
後の平面図、第３図はＴＡＢリード型半導体装置
の構造例を示す平面図、第４図は第３図の断面図
、第５図は半導体中間構体の従来例を示す平面図
、第６図は第５図のテープ部分から切断された中
間構体を特性試験するＢＴボードを示す斜視図で
ある。
３…金属箔リード、４…半導体ペレツト、７…
絶縁性テープ、８…角孔、１５…メツキ処理用導
電パターン、１６…給電用配線、１７…リード引
出し用配線、Ｂ…半導体中間構体。
1 and 2 are plan views showing one embodiment of a semiconductor intermediate structure according to the present invention before and after plating processing, and FIG. 3 is a plan view showing an example of the structure of a TAB lead type semiconductor device. 4 is a sectional view of FIG. 3, FIG. 5 is a plan view showing a conventional example of a semiconductor intermediate structure, and FIG. 6 is a perspective view showing a BT board for testing the characteristics of the intermediate structure cut from the tape portion of FIG. It is a diagram. 3...Metal foil lead, 4...Semiconductor pellet, 7...
Insulating tape, 8... Square hole, 15... Conductive pattern for plating processing, 16... Wiring for power supply, 17... Wiring for lead extraction, B... Semiconductor intermediate structure.
Claims (1)
毎に設けられた複数の孔と、これらの孔内に配置
された複数の半導体ペレツトと、上記孔の周縁部
に放射状に形成され、孔内に延びた一端が上記半
導体ペレツトのバンプ電極に圧着された複数の金
属箔リードと、テープの孔周縁部に形成され、金
属箔リードをメツキ処理するためのメツキ処理用
導電パターンとからなるものにおいて、 上記メツキ処理用導電パターンを上記テープの
長手方向並びに短手方向に夫々設けた１本の給電
用配線の途中から各金属箔リードの電極パツドに
接続された複数本のリード引出し用配線を分岐さ
せて構成したことを特徴とする半導体中間構体。[Claims for Utility Model Registration] A long insulating tape, a plurality of holes provided in the tape at predetermined intervals, a plurality of semiconductor pellets placed in these holes, and the peripheral edges of the holes. A plurality of metal foil leads are formed radially in the hole and one end extending into the hole is crimped to the bump electrode of the semiconductor pellet, and a plating process is formed around the hole periphery of the tape to plate the metal foil leads. A plurality of conductive patterns for plating are connected to the electrode pads of each metal foil lead from the middle of one power supply wiring provided in the longitudinal direction and short direction of the tape, respectively. A semiconductor intermediate structure characterized in that the wiring for leading out a book is configured by branching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986193175U JPS6397235U (en) | 1986-12-15 | 1986-12-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986193175U JPS6397235U (en) | 1986-12-15 | 1986-12-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6397235U true JPS6397235U (en) | 1988-06-23 |
Family
ID=31148954
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986193175U Pending JPS6397235U (en) | 1986-12-15 | 1986-12-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6397235U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998018163A1 (en) * | 1996-10-22 | 1998-04-30 | Seiko Epson Corporation | Film carrier tape, tape carrier semiconductor device assembly, semiconductor device, its manufacturing method, package substrate, and electronic appliance |
| WO1998033212A1 (en) * | 1997-01-23 | 1998-07-30 | Seiko Epson Corporation | Film carrier tape, semiconductor assembly, semiconductor device, manufacturing method therefor, mounting board, and electronic equipment |
-
1986
- 1986-12-15 JP JP1986193175U patent/JPS6397235U/ja active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998018163A1 (en) * | 1996-10-22 | 1998-04-30 | Seiko Epson Corporation | Film carrier tape, tape carrier semiconductor device assembly, semiconductor device, its manufacturing method, package substrate, and electronic appliance |
| KR100455492B1 (en) * | 1996-10-22 | 2005-01-13 | 세이코 엡슨 가부시키가이샤 | Film carrier tape and its manufacturing method, tape carrier semiconductor device assembly manufacturing method, semiconductor device and its manufacturing method, mounting board and electronic equipment |
| SG165145A1 (en) * | 1996-10-22 | 2010-10-28 | Seiko Epson Corp | Film carrier tape |
| WO1998033212A1 (en) * | 1997-01-23 | 1998-07-30 | Seiko Epson Corporation | Film carrier tape, semiconductor assembly, semiconductor device, manufacturing method therefor, mounting board, and electronic equipment |