JPS5999448U - Chippukiyariya - Google Patents
ChippukiyariyaInfo
- Publication number
- JPS5999448U JPS5999448U JP19905382U JP19905382U JPS5999448U JP S5999448 U JPS5999448 U JP S5999448U JP 19905382 U JP19905382 U JP 19905382U JP 19905382 U JP19905382 U JP 19905382U JP S5999448 U JPS5999448 U JP S5999448U
- Authority
- JP
- Japan
- Prior art keywords
- terminals provided
- chip carrier
- chippukiyariya
- ceramic
- green
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は切裁断面を含む従来の単層セラミックのチップ
キャリアの斜視図、第２図は基板内多層配線基板を用い
た従来のチップキャリアの切裁断面を含む斜視図、第３
図は本考案の一実施例の切裁断面を含む斜視図である。
１．１１・・・・・・チップキャリア本体、２・・・・
・・導体、３・・・・・・側面端子、３ａ・・・・・・
周辺端子のバンプ、４・・・・・・ワイヤボンディング
ランド、５・・・・・・グイボンディングランド、６・
・・・・・スルーホール部、７・・・・・・内側端子の
バンプ。FIG. 1 is a perspective view of a conventional single-layer ceramic chip carrier including a cut cross section, FIG. 2 is a perspective view including a cut cross section of a conventional chip carrier using a multilayer wiring board within the board, and FIG.
The figure is a perspective view including a cut section of an embodiment of the present invention. 1.11...Chip carrier body, 2...
...Conductor, 3...Side terminal, 3a...
Bump of peripheral terminal, 4... Wire bonding land, 5... Gui bonding land, 6.
...Through hole part, 7...Bump of inner terminal.
Claims (1)
層配線回路を形成してセラミックと導体層を同時に焼成
させた基板内多層配線基板を用いて形成され、かつ、チ
ップ搭載面の反対側（裏面）周辺に設けられた多数の端
子に加えその内側にもさらに複数の端子が設けられてい
ることを特徴きするチップキャリア。A multilayer wiring circuit is formed in the state of a green ceramic board (green sheet) before firing, and the ceramic and conductor layers are simultaneously fired. ) A chip carrier characterized by having a plurality of terminals provided on the inside in addition to a large number of terminals provided around the periphery.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19905382U JPS5999448U (en) | 1982-12-23 | 1982-12-23 | Chippukiyariya |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19905382U JPS5999448U (en) | 1982-12-23 | 1982-12-23 | Chippukiyariya |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5999448U true JPS5999448U (en) | 1984-07-05 |
Family
ID=30424604
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19905382U Pending JPS5999448U (en) | 1982-12-23 | 1982-12-23 | Chippukiyariya |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5999448U (en) |
-
1982
- 1982-12-23 JP JP19905382U patent/JPS5999448U/en active Pending
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