JPS62135440U - - Google Patents
Info
- Publication number
- JPS62135440U JPS62135440U JP2480286U JP2480286U JPS62135440U JP S62135440 U JPS62135440 U JP S62135440U JP 2480286 U JP2480286 U JP 2480286U JP 2480286 U JP2480286 U JP 2480286U JP S62135440 U JPS62135440 U JP S62135440U
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- wiring board
- printed wiring
- hole
- conductor pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 2
- 229910052709 silver Inorganic materials 0.000 claims description 2
- 239000004332 silver Substances 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims 2
- 239000004065 semiconductor Substances 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 description 1
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図及び第２図はこの考案の一実施例を示す
断面図、第３図乃至第５図は従来例を示す図で、
第３図及び第４図は断面図、第５図は平面図であ
る。
１は端子、２はスルホール、３は半田、４はダ
イパツド部、５は導体パターン、６はプリント配
線基板、７は銀ペーストである。
Figures 1 and 2 are cross-sectional views showing an embodiment of this invention, and Figures 3 to 5 are views showing conventional examples.
3 and 4 are cross-sectional views, and FIG. 5 is a plan view. 1 is a terminal, 2 is a through hole, 3 is solder, 4 is a die pad portion, 5 is a conductive pattern, 6 is a printed wiring board, and 7 is a silver paste.
Claims (1)
するダイパツド部４を形成し、周辺の裏面にピン
状の端子１を突設せるピングリツドアレイにおい
て、プリント配線基板６に形成した導体パターン
５にスルホール２を挿通固定し、スルホール２に
端子１を挿通すると共に該スルホール２と端子１
及び導体パターン５とを銀ペースト７で接続して
なるピングリツドアレイ。 In a pin grid array in which a die pad part 4 on which a semiconductor element is mounted is formed in the center of a printed wiring board 6, and pin-shaped terminals 1 are protruded from the back surface of the periphery, through holes are formed in a conductor pattern 5 formed on the printed wiring board 6. 2 and then insert the terminal 1 into the through hole 2 and connect the through hole 2 and the terminal 1.
and a conductor pattern 5 are connected with a silver paste 7 to form a pin grid array.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2480286U JPS62135440U (en) | 1986-02-21 | 1986-02-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2480286U JPS62135440U (en) | 1986-02-21 | 1986-02-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62135440U true JPS62135440U (en) | 1987-08-26 |
Family
ID=30824360
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2480286U Pending JPS62135440U (en) | 1986-02-21 | 1986-02-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62135440U (en) |
-
1986
- 1986-02-21 JP JP2480286U patent/JPS62135440U/ja active Pending