JPS6324838U - - Google Patents
Info
- Publication number
- JPS6324838U JPS6324838U JP1986118453U JP11845386U JPS6324838U JP S6324838 U JPS6324838 U JP S6324838U JP 1986118453 U JP1986118453 U JP 1986118453U JP 11845386 U JP11845386 U JP 11845386U JP S6324838 U JPS6324838 U JP S6324838U
- Authority
- JP
- Japan
- Prior art keywords
- chip component
- recess
- carrier
- mounting structure
- component mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004020 conductor Substances 0.000 claims description 3
- 239000011093 chipboard Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図のａ，ｂ，ｃは本考案の実施例の断面図
、第２図は従来例の斜視図、第３図は従来例の側
断面図である。
図において、１はチツプ部品、２はチツプ基板
、３は電極、３Ａは電極端末、５はキヤリア、６
はキヤビテイ、７はパターン、８は側面パターン
、９はパツド、１０は基板、２０は凹部、２０Ａ
，２０Ｂは側面開口凹部、２５は充填導体、２５
Ａは導体粒を示す。
1A, B, and C are sectional views of the embodiment of the present invention, FIG. 2 is a perspective view of the conventional example, and FIG. 3 is a side sectional view of the conventional example. In the figure, 1 is a chip component, 2 is a chip board, 3 is an electrode, 3A is an electrode terminal, 5 is a carrier, and 6
is the cavity, 7 is the pattern, 8 is the side pattern, 9 is the pad, 10 is the board, 20 is the recess, 20A
, 20B is a side opening recess, 25 is a filled conductor, 25
A indicates a conductor grain.
Claims (1)
品１を収容し、該キヤリア５及びチツプ部品１上
のパターン３，７を結合してなるチツプ部品の実
装構造において、 該キヤリア５及び該チツプ部品１のそれぞれの
パターンに対応した側壁部に、凹部２０を設け、 該凹部２０に導体材料を充填したことを特徴と
するチツプ部品の実装構造。[Scope of Claim for Utility Model Registration] A chip component mounting structure in which a chip component 1 is housed in a cavity 6 formed in a carrier 5, and patterns 3 and 7 on the carrier 5 and the chip component 1 are combined, 5 and a chip component mounting structure characterized in that a recess 20 is provided in a side wall portion corresponding to each pattern of the chip component 1, and the recess 20 is filled with a conductive material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986118453U JPH0438522Y2 (en) | 1986-08-01 | 1986-08-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986118453U JPH0438522Y2 (en) | 1986-08-01 | 1986-08-01 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6324838U true JPS6324838U (en) | 1988-02-18 |
| JPH0438522Y2 JPH0438522Y2 (en) | 1992-09-09 |
Family
ID=31004918
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986118453U Expired JPH0438522Y2 (en) | 1986-08-01 | 1986-08-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0438522Y2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1994029887A1 (en) * | 1993-06-14 | 1994-12-22 | Poripurasuchikkusu Co., Ltd. | Molded electric part and its manufacture |
| EP3542398A4 (en) * | 2016-11-21 | 2020-12-02 | 3M Innovative Properties Company | Automatic registration between circuit dies and interconnects |
-
1986
- 1986-08-01 JP JP1986118453U patent/JPH0438522Y2/ja not_active Expired
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1994029887A1 (en) * | 1993-06-14 | 1994-12-22 | Poripurasuchikkusu Co., Ltd. | Molded electric part and its manufacture |
| EP3542398A4 (en) * | 2016-11-21 | 2020-12-02 | 3M Innovative Properties Company | Automatic registration between circuit dies and interconnects |
| US10971468B2 (en) | 2016-11-21 | 2021-04-06 | 3M Innovative Properties Company | Automatic registration between circuit dies and interconnects |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0438522Y2 (en) | 1992-09-09 |