JPH0438522Y2 - - Google Patents
Info
- Publication number
- JPH0438522Y2 JPH0438522Y2 JP1986118453U JP11845386U JPH0438522Y2 JP H0438522 Y2 JPH0438522 Y2 JP H0438522Y2 JP 1986118453 U JP1986118453 U JP 1986118453U JP 11845386 U JP11845386 U JP 11845386U JP H0438522 Y2 JPH0438522 Y2 JP H0438522Y2
- Authority
- JP
- Japan
- Prior art keywords
- carrier
- pattern
- chip component
- recess
- cavity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004020 conductor Substances 0.000 claims description 15
- 239000000758 substrate Substances 0.000 description 10
- 229910000679 solder Inorganic materials 0.000 description 5
- 239000000919 ceramic Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 239000011093 chipboard Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229910000927 Ge alloy Inorganic materials 0.000 description 1
- BYDQGSVXQDOSJJ-UHFFFAOYSA-N [Ge].[Au] Chemical compound [Ge].[Au] BYDQGSVXQDOSJJ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
Description
【考案の詳細な説明】
〔概要〕
チツプ部品とキヤリアの境界線部に、電極端末
とパターン端末とを対向して備えた凹部を設け、
凹部に導体材料を充填して電極とパターンとを接
続することにより、キヤリア内の特性インピーダ
ンスと、外部線路の特性インピーダンスとの整合
を容易にとれるようにする。[Detailed explanation of the invention] [Summary] A recessed portion with an electrode terminal and a pattern terminal facing each other is provided at the boundary between the chip component and the carrier,
By filling the recess with a conductive material and connecting the electrode and the pattern, the characteristic impedance inside the carrier and the characteristic impedance of the external line can be easily matched.
本考案は、IC，LSI，混成集積回路等のチツプ
部品の実装構造の改良に関する。
This invention relates to improvements in the mounting structure of chip components such as ICs, LSIs, and hybrid integrated circuits.
IC，LSI，混成集積回路等のチツプ部品を、上
面、側壁、及び底面に導体膜よりなるパターンを
設けたセラミツクよりなるキヤリアに実装したリ
ードレス型の電子部品は、基板の表面に形成した
基板パターンに直接半田付接続することができ、
且つ基板に高密度に搭載することができるので、
電子装置に広く使用されている。 Leadless electronic components, in which chip components such as ICs, LSIs, and hybrid integrated circuits are mounted on carriers made of ceramic with patterns of conductive films on the top, side walls, and bottom, are manufactured by mounting chip components such as Can be soldered directly to the pattern,
In addition, it can be mounted on the board with high density,
Widely used in electronic devices.
第２図及び第３図を参照しながら、従来のチツ
プ部品の実装構造を説明する。
A conventional chip component mounting structure will be described with reference to FIGS. 2 and 3.
第２図は従来例の斜視図、第３図は従来例の側
断面図であつて、チツプ部品１は、チツプ基板２
の上面に所望の回路素子が形成されており、周縁
部の上面にキヤリア５のパターン７に接続する電
極３を放射状に設けてある。 FIG. 2 is a perspective view of the conventional example, and FIG. 3 is a side sectional view of the conventional example.
Desired circuit elements are formed on the upper surface, and electrodes 3 connected to the pattern 7 of the carrier 5 are provided radially on the upper surface of the peripheral portion.
また、チツプ部品１を実装するキヤリア５は、
セラミツク、例えばアルミナよりなる小さい角板
形で、中央部に段付角形のキヤビテイ６を設けて
ある。キヤリア５の底面に平行するキヤビテイ６
の段端面には、キヤビテイ６のそれぞれの辺に直
交して放射状に、キヤリア５の側壁に形成した側
面パターン８に連結する金属導体膜よりなるパタ
ーン７が形成されている。また、キヤリア５の底
面の周縁には、それぞれの側面パターン８に連結
した、金属導体膜よりなる角片形のパツド９を形
成してある。 In addition, the carrier 5 on which the chip component 1 is mounted is
It is a small square plate made of ceramic, for example alumina, and has a stepped square cavity 6 in the center. Cavity 6 parallel to the bottom of carrier 5
A pattern 7 made of a metal conductor film is formed on the step end surface of the carrier 5 in a radial direction perpendicular to each side of the cavity 6 and connected to a side pattern 8 formed on the side wall of the carrier 5. Further, on the periphery of the bottom surface of the carrier 5, a rectangular piece-shaped pad 9 made of a metal conductive film and connected to each side pattern 8 is formed.
上述のように構成されたキヤリア５のキヤビテ
イ６の底面に、チツプ部品１を供晶合金手段、或
いは半田接続手段等により搭載固着し、その後、
直径が例えば25μm程度の金線等の接続線１５を
ワイヤボンデングして、対応するそれぞれの電極
３とパターン７とを接続している。 The chip component 1 is mounted and fixed on the bottom surface of the cavity 6 of the carrier 5 configured as described above using a donor alloy means, solder connection means, etc., and then,
Each corresponding electrode 3 and pattern 7 are connected by wire bonding a connecting wire 15 such as a gold wire having a diameter of about 25 μm, for example.
そして、キヤリア５の開放された上端面に、セ
ラミツク板、或いは金属板よりなるカバー１９を
接着し、チツプ部品１を封止している。 Then, a cover 19 made of a ceramic plate or a metal plate is adhered to the open upper end surface of the carrier 5 to seal the chip component 1.
一方、基板１０の表面に、電極３の数量に等し
い数量の基板パターン１１を形成し、それぞれの
基板パターン１１の端部には、キヤリア５のパツ
ド９に対応して基板パツドを配設してある。 On the other hand, the number of substrate patterns 11 equal to the number of electrodes 3 is formed on the surface of the substrate 10, and substrate pads are arranged at the ends of each substrate pattern 11 in correspondence with the pads 9 of the carrier 5. be.
上述のようにキヤリア５にチツプ部品１を実装
した電子部品を、基板１０に半田付け搭載するに
は、基板パツドの上面に半田ペーストを、例えば
スクリーン印刷し、基板パツドにキヤリア５のパ
ツド９を位置合わせして、電子部品を基板１０に
仮設置し、基板１０を例えば赤外線加熱炉等に入
れて加熱する。 In order to solder and mount an electronic component in which the chip component 1 is mounted on the carrier 5 onto the board 10 as described above, a solder paste is, for example, screen printed on the top surface of the board pad, and the pad 9 of the carrier 5 is attached to the board pad. After alignment, the electronic components are temporarily installed on the board 10, and the board 10 is placed in, for example, an infrared heating furnace and heated.
加熱すると半田ペーストがリフローして、パツ
ド９に密着すると同時に、溶融状態の半田が側面
パターン８沿つて立ち上がり側面パターン８にも
密着する。 When heated, the solder paste reflows and comes into close contact with the pad 9, and at the same time, the molten solder rises along the side pattern 8 and also comes into close contact with the side pattern 8.
しかしながら上記従来例のように、電極３とパ
ターン７とを接続線１５を介して接続した実装手
段は、キヤリア５内の配線パターンの特性インピ
ーダンスと基板１０上の外部線路との特性インピ
ーダンスとを等しく設計しても、接続線１５の長
さの不揃い、配線形状の不揃い等に起因して、接
続線１５部分のインピーダンスが大きくなる。
However, as in the above conventional example, the mounting means in which the electrode 3 and the pattern 7 are connected via the connection line 15 makes the characteristic impedance of the wiring pattern in the carrier 5 equal to the characteristic impedance of the external line on the board 10. Even when designed, the impedance of the connection line 15 portion becomes large due to irregularities in the length of the connection line 15, irregularity in the shape of the wiring, and the like.
したがつて、キヤリア５の内外の特性インピー
ダンスが異なる値となり、チツプ部品１の所望の
特性を外部に引き出すことができないという問題
点がある。 Therefore, the internal and external characteristic impedances of the carrier 5 have different values, and there is a problem that the desired characteristics of the chip component 1 cannot be brought out to the outside.
上記従来の問題点を解決するため本考案は、電
極端末３Ａを備えた側面開口凹部２０Ａをチツプ
基板２の周縁に設け、一方、キヤリア５の上面の
パターン７に連結したパターン端末７Ａを備えた
側面開口凹部２０Ｂを、側面開口凹部２０Ａに対
向して、キヤビテイ６の内壁に設けて、チツプ部
品１とキヤリア５との境界線部に凹部２０を構成
させてある。
In order to solve the above conventional problems, the present invention provides a side opening recess 20A with an electrode terminal 3A on the periphery of the chip substrate 2, and a pattern terminal 7A connected to the pattern 7 on the upper surface of the carrier 5. A side-opening recess 20B is provided on the inner wall of the cavity 6 opposite to the side-opening recess 20A, and the recess 20 is formed at the boundary between the chip component 1 and the carrier 5.
そして、それぞれの凹部２０に導体粒２５Ａを
充填し、この導体粒２５Ａを溶融させて、充填導
体２５により、電極３とパターン７とを接続した
ものである。 Then, each recess 20 is filled with conductor grains 25A, and the conductor grains 25A are melted to connect the electrode 3 and the pattern 7 through the filled conductor 25.
上記本考案によれば、チツプ基板２の外形寸法
をキヤビテイ６の内形寸法よりもわずかに小さく
して、チツプ部品１とキヤリア５との間隙を狭く
することは容易であるので、凹部２０に充填した
充填導体２５のインピーダンスは無視し得るほど
小さい。よつて、予め電極３を含めたキヤリア５
の配線パターンの特性インピーダンスを、外部線
路の特性インピーダンスに等しく設計することに
より、設計値に等しい特性インピーダンスが得ら
れる。
According to the present invention, it is easy to narrow the gap between the chip component 1 and the carrier 5 by making the external dimensions of the chip board 2 slightly smaller than the internal dimensions of the cavity 6. The impedance of the filled conductor 25 is negligibly small. Therefore, the carrier 5 including the electrode 3 in advance
By designing the characteristic impedance of the wiring pattern to be equal to the characteristic impedance of the external line, a characteristic impedance equal to the designed value can be obtained.
よつて、キヤリア５の特性インピーダンスと外
部線路の特性インピーダンスとの整合がとれ、チ
ツプ部品１の所望の特性を外部に引き出すことが
できる。 Therefore, the characteristic impedance of the carrier 5 and the characteristic impedance of the external line can be matched, and desired characteristics of the chip component 1 can be brought out to the outside.
以下図を参照しながら、本考案を具体的に説明
する。なお、全図を通じて同一符号は同一対象物
を示す。
The present invention will be specifically explained below with reference to the drawings. Note that the same reference numerals indicate the same objects throughout the figures.
第１図のａ，ｂ，ｃは本考案の一実施例の断面
図である。 Figures a, b, and c in Fig. 1 are cross-sectional views of an embodiment of the present invention.
本考案は、下記の如くにして製造されたもので
ある。 The present invention was manufactured as follows.
第１図ａのように、チツプ基板２の周縁に、外
側が開口した側面開口凹部２０Ａを並列して設け
てある。そして、チツプ基板２の周縁部の上面に
放射状に設けた電極３を、それぞれの側面開口凹
部２０Ａ内に延伸し、側面開口凹部２０Ａの底面
に電極端末３Ａを設けてある。 As shown in FIG. 1a, side-opening recesses 20A, which are open on the outside, are provided in parallel on the periphery of the chip substrate 2. Electrodes 3 provided radially on the upper surface of the peripheral edge of the chip substrate 2 are extended into the respective side opening recesses 20A, and electrode terminals 3A are provided on the bottom surfaces of the side opening recesses 20A.
チツプ部品１を実装するキヤリア５は、セラミ
ツク、例えばアルミナよりなり、中央部にキヤビ
テイ６を設けてある。キヤビテイ６の内形寸法
は、チツプ部品１が実装された状態で、チツプ基
板２の側面とキヤビテイ６の内壁との間隙が、例
えば30μm程度となるような寸法である。 The carrier 5 on which the chip component 1 is mounted is made of ceramic, for example alumina, and has a cavity 6 in the center. The internal dimensions of the cavity 6 are such that, when the chip component 1 is mounted, the gap between the side surface of the chip substrate 2 and the inner wall of the cavity 6 is, for example, about 30 μm.
キヤビテイ６の内壁には、それぞれの側面開口
凹部２０Ａに対向して、内側が開口した側面開口
凹部２０Ｂを設け、キヤビテイ６のそれぞれの辺
に直交した放射状のパターン７を、それぞれの側
面開口凹部２０Ｂ内に延伸し、側面開口凹部２０
Ｂの底面にパターン端末７Ａを設けてある。 A side opening recess 20B with an open inner side is provided on the inner wall of the cavity 6, facing each side opening recess 20A, and a radial pattern 7 perpendicular to each side of the cavity 6 is formed in each side opening recess 20B. Extending inward, side opening recess 20
A pattern terminal 7A is provided on the bottom surface of B.
したがつて、チツプ部品１をキヤビテイ６内に
実装すると、チツプ部品１とキヤリア５との境界
線部に所望数の上方が開口した凹部２０が構成さ
れ並設される。なお、この凹部２０の深さは数十
μm乃至数百μmであり、底面積は例えば100μm2で
ある。 Therefore, when the chip component 1 is mounted in the cavity 6, a desired number of recesses 20 having an upward opening are formed at the boundary line between the chip component 1 and the carrier 5 and are arranged in parallel. Note that the depth of the recess 20 is several tens of μm to several hundred μm, and the bottom area is, for example, 100 μm 2 .
また、第１図ｂ，ｃに示すように、それぞれの
パターン７は、キヤリア５の側壁に形成した側面
パターン８に連結し、側面パターン８の下縁は、
キヤリア５の底面の周縁に並設したパツド９に連
結している。 Further, as shown in FIGS. 1b and 1c, each pattern 7 is connected to a side pattern 8 formed on the side wall of the carrier 5, and the lower edge of the side pattern 8 is
It is connected to pads 9 arranged in parallel on the periphery of the bottom surface of the carrier 5.
上述のように、側面開口凹部２０Ａと側面開口
凹部２０Ｂとで構成された凹部２０に、第１図ｂ
に示すように、例えば金・ゲルマニユム合金（融
点は380℃）よりなる導体粒２５Ａを充填する。 As described above, in the recess 20 composed of the side opening recess 20A and the side opening recess 20B, the recess 20 shown in FIG.
As shown in the figure, conductor grains 25A made of, for example, a gold-germanium alloy (melting point: 380° C.) are filled.
そして、キヤリア５の上方より、例えばYAG
レーザーを導体粒２５Ａに照射する。 Then, from above the carrier 5, for example, YAG
The conductor grains 25A are irradiated with a laser.
このことにより、ほぼ0.1秒の照射時間で、導
体粒２５Ａが溶融して、第１図ｃの如くに、凹部
２０内に充填導体２５が充填され、電極端末３Ａ
とパターン端末７Ａとが接続される。 As a result, the conductor grains 25A are melted in an irradiation time of approximately 0.1 seconds, and the recess 20 is filled with the filling conductor 25, as shown in FIG. 1c, and the electrode terminal 3A
and pattern terminal 7A are connected.
なお、導体粒２５Ａが溶融しても、チツプ基板
２とキヤビテイ６との間隙が小さく、且つ凹部２
０は上方が開口しているだけであるので、隣接し
たパターン７、電極３に短絡する恐れがない。 Note that even if the conductor grains 25A melt, the gap between the chip substrate 2 and the cavity 6 is small and the recess 2
0 is only open at the top, so there is no risk of short-circuiting to the adjacent pattern 7 or electrode 3.
以上説明したように本考案は、キヤリアとチツ
プ部品との境界線部に設けた凹部に、電極とパタ
ーンとを延伸して形成し、凹部に溶融充填させた
充填導体で、電極とパターンとを接続するように
構成されたもので、キヤリア内の特性インピーダ
ンスを所定値にすることが容易で、外部線路との
整合度が高く、チツプ部品の特性を満足できる高
特性で、外部に引き出すことができるという優れ
た効果がある。
As explained above, in the present invention, an electrode and a pattern are stretched and formed in a recess provided at the boundary between a carrier and a chip component, and a filled conductor is melted and filled into the recess to connect the electrode and pattern. It is configured to be connected, it is easy to set the characteristic impedance inside the carrier to a predetermined value, it has a high degree of matching with external lines, it has high characteristics that satisfy the characteristics of chip components, and it can be extracted externally. There is an excellent effect that can be done.
第１図のａ，ｂ，ｃは本考案の実施例の断面
図、第２図は従来例の斜視図、第３図は従来例の
側断面図である。
図において、１はチツプ部品、２はチツプ基
板、３は電極、３Ａは電極端末、５はキヤリア、
６はキヤビテイ、７はパターン、８は側面パター
ン、９はパツド、１０は基板、２０は凹部、２０
Ａ，２０Ｂは側面開口凹部、２５は充填導体、２
５Ａは導体粒を示す。
1A, B, and C are sectional views of the embodiment of the present invention, FIG. 2 is a perspective view of the conventional example, and FIG. 3 is a side sectional view of the conventional example. In the figure, 1 is a chip component, 2 is a chip board, 3 is an electrode, 3A is an electrode terminal, 5 is a carrier,
6 is a cavity, 7 is a pattern, 8 is a side pattern, 9 is a pad, 10 is a substrate, 20 is a recess, 20
A, 20B are side opening recesses, 25 is a filled conductor, 2
5A indicates a conductor grain.
Claims (1)
品１を収容し、該キヤリア５及びチツプ部品１上
のパターン３，７を結合してなるチツプ部品の実
装構造において、 該キヤリア５及び該チツプ部品１のそれぞれの
パターンに対応した側壁部に、凹部２０を設け、 該凹部２０に導体材料を充填したことを特徴と
するチツプ部品の実装構造。[Scope of Claim for Utility Model Registration] A chip component mounting structure in which a chip component 1 is housed in a cavity 6 formed in a carrier 5, and patterns 3 and 7 on the carrier 5 and the chip component 1 are combined, 5 and a chip component mounting structure characterized in that a recess 20 is provided in a side wall portion corresponding to each pattern of the chip component 1, and the recess 20 is filled with a conductive material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986118453U JPH0438522Y2 (en) | 1986-08-01 | 1986-08-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986118453U JPH0438522Y2 (en) | 1986-08-01 | 1986-08-01 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6324838U JPS6324838U (en) | 1988-02-18 |
| JPH0438522Y2 true JPH0438522Y2 (en) | 1992-09-09 |
Family
ID=31004918
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986118453U Expired JPH0438522Y2 (en) | 1986-08-01 | 1986-08-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0438522Y2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3323958B2 (en) * | 1993-06-14 | 2002-09-09 | ポリプラスチックス株式会社 | Manufacturing method of molded electric parts |
| WO2018094057A1 (en) * | 2016-11-21 | 2018-05-24 | 3M Innovative Properties Company | Automatic registration between circuit dies and interconnects |
-
1986
- 1986-08-01 JP JP1986118453U patent/JPH0438522Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6324838U (en) | 1988-02-18 |
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