JPS6389254U - - Google Patents

Info

Publication number
JPS6389254U
JPS6389254U JP18345186U JP18345186U JPS6389254U JP S6389254 U JPS6389254 U JP S6389254U JP 18345186 U JP18345186 U JP 18345186U JP 18345186 U JP18345186 U JP 18345186U JP S6389254 U JPS6389254 U JP S6389254U
Authority
JP
Japan
Prior art keywords
package
contact member
transfer mold
circuits
sealed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18345186U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18345186U priority Critical patent/JPS6389254U/ja
Publication of JPS6389254U publication Critical patent/JPS6389254U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の一実施例を示す断面図、第２
図ａ，ｂ，ｃは本考案に係る弾性部材７の３例を
示す正面図、第３図乃至第５図は本考案による半
導体パツケージけの適用例及び実装例を示す断面
図及び斜視図、第６図乃至第８図は夫々従来の半
導体パツケージを示す図である。 １……金属基板、２……半導体、３……電子部
品、４……ワイヤーボンド、５……リードフレー
ム、６……接点部材、７……弾性部材、８……ト
ランスフアーモールド樹脂。 Fig. 1 is a sectional view showing one embodiment of the present invention;
Figures a, b, and c are front views showing three examples of the elastic member 7 according to the present invention, and Figures 3 to 5 are sectional views and perspective views showing application examples and mounting examples of the semiconductor package holder according to the present invention. FIGS. 6 to 8 are views showing conventional semiconductor packages, respectively. DESCRIPTION OF SYMBOLS 1... Metal substrate, 2... Semiconductor, 3... Electronic component, 4... Wire bond, 5... Lead frame, 6... Contact member, 7... Elastic member, 8... Transfer mold resin.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 電子部品、回路等を樹脂によつて封止したトラ
ンスフアーモールドパツケージにおいて、パツケ
ージの少なくとも一面に機構部品の一部を成すと
共にパツケージ内の回路等に電気的に接続された
接点部材を露出させたことを特徴とする半導体パ
ツケージ。 In a transfer mold package in which electronic components, circuits, etc. are sealed with resin, a contact member that forms part of a mechanical component and is electrically connected to a circuit, etc. inside the package is exposed on at least one surface of the package. A semiconductor package characterized by:
JP18345186U 1986-11-28 1986-11-28 Pending JPS6389254U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18345186U JPS6389254U (en) 1986-11-28 1986-11-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18345186U JPS6389254U (en) 1986-11-28 1986-11-28

Publications (1)

Publication Number Publication Date
JPS6389254U true JPS6389254U (en) 1988-06-10

Family

ID=31130199

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18345186U Pending JPS6389254U (en) 1986-11-28 1986-11-28

Country Status (1)

Country Link
JP (1) JPS6389254U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008227131A (en) * 2007-03-13 2008-09-25 Renesas Technology Corp Semiconductor device and its manufacturing method
JP2013171848A (en) * 2012-02-17 2013-09-02 Denso Corp Mold package and manufacturing method thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56155555A (en) * 1980-05-06 1981-12-01 Seiko Epson Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56155555A (en) * 1980-05-06 1981-12-01 Seiko Epson Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008227131A (en) * 2007-03-13 2008-09-25 Renesas Technology Corp Semiconductor device and its manufacturing method
JP2013171848A (en) * 2012-02-17 2013-09-02 Denso Corp Mold package and manufacturing method thereof

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