JPS6386496A - Manufacture of printed circuit board - Google Patents
Manufacture of printed circuit boardInfo
- Publication number
- JPS6386496A JPS6386496A JP23011986A JP23011986A JPS6386496A JP S6386496 A JPS6386496 A JP S6386496A JP 23011986 A JP23011986 A JP 23011986A JP 23011986 A JP23011986 A JP 23011986A JP S6386496 A JPS6386496 A JP S6386496A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- conductive paste
- circuit board
- printed circuit
- insulating substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 10
- 238000007639 printing Methods 0.000 claims description 9
- 239000004020 conductor Substances 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000005553 drilling Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 238000005266 casting Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000009281 ultraviolet germicidal irradiation Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
本発明は、印刷回路基板の製造方法に係り、特に、印刷
による多層回路の重ね刷りを減少させ、できるだけ平滑
な条件に印刷し膜厚を低減しピンホールを減少させよう
とする印刷回路基板の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a printed circuit board, and in particular, it reduces overprinting of multilayer circuits by printing, prints under as smooth conditions as possible, reduces film thickness, and reduces pinholes. The present invention relates to a method of manufacturing a printed circuit board.
従来のこの種の印刷回路基板の製造方法においては、例
えば、その−例を第5図に示すように、印刷にて多層回
路を形成するとなると、たかだか導電層を2層だけ形成
するのに9回の印刷が必要となる。In the conventional manufacturing method of this type of printed circuit board, for example, when forming a multilayer circuit by printing, as shown in FIG. Requires multiple printings.
すなわち、このような従来技術の問題点は次の如くであ
った。That is, the problems with such conventional technology are as follows.
1) たかだか2層の回路形成を行なうのに、9回以上
の重ね刷りが必要となることから、位置決め精度により
回路信顛性が大きく変ってきて、ファインパターン化の
足をひっばる。1) Since overprinting is required nine times or more to form a circuit of at most two layers, the circuit reliability changes greatly depending on the positioning accuracy, which hinders the creation of fine patterns.
2) 重ね刷り工程が多くなることにより、コストも高
くなる。2) As the number of overprinting steps increases, the cost also increases.
3) さらに多くの多層化が望めない。3) More multi-layering cannot be expected.
4) 実際には、第5図に示すようなきれいな印刷断面
が得られず、その上、重ね刷りして行くことから、表面
の凹凸がはげしくなり、印刷したものの膜厚及びピンホ
ールの管理ができなくなる。4) In reality, it is not possible to obtain a clean printed cross-section as shown in Figure 5, and on top of that, since overprinting is performed, the surface becomes extremely uneven, making it difficult to control the film thickness and pinholes of the printed material. become unable.
本発明は、このような従来方法における問題点を解決し
、印刷による多層回路の重ね刷りを減少させ、できるだ
け平滑な条件に印刷し膜厚を低減しピンホールを減少さ
せる印刷回路基板の製造方法を提供しようとするもので
ある。The present invention solves the problems in the conventional methods, and provides a method for manufacturing printed circuit boards that reduces overprinting of multilayer circuits by printing, prints under as smooth conditions as possible, reduces film thickness, and reduces pinholes. This is what we are trying to provide.
本発明方法は、その実施例が図面にもみられるように、
導電ペーストにより所望パターンの回路導体を絶縁基板
上に印刷にて形成する印刷回路基板の製造方法において
、絶縁基板に予め所定の基準孔及び/又はスルーホール
の孔加工を行ない、少なくとも基板の片面上に回路形成
用の感光性レジストをかけ、これを所定のマスクを通し
て露光し現像して、所定のパターンの回路溝を形成し、
該回路溝に直かに導電ペーストを流し込んで、導電ペー
ストにより所望パターンの回路導体を絶縁基板上に印刷
にて形成することを特徴とする。As examples of the method of the present invention can be seen in the drawings,
In a method of manufacturing a printed circuit board in which a circuit conductor in a desired pattern is printed on an insulating substrate using conductive paste, the insulating substrate is pre-drilled with predetermined reference holes and/or through holes, and the circuit conductors are formed on at least one side of the substrate. A photosensitive resist for circuit formation is applied to the wafer, and this is exposed through a prescribed mask and developed to form circuit grooves in a prescribed pattern.
The present invention is characterized in that a conductive paste is poured directly into the circuit groove, and a circuit conductor of a desired pattern is formed by printing on the insulating substrate using the conductive paste.
すなわち、ガラスエポキシ板、又はポリイミド板等の絶
縁基板1に基準孔及びスルーホール孔2あけ加工をした
後、前述のようにフォトレジスト3によるマスク4を形
成し、この溝5に導電ペースト6をロールコータ−(図
示せず)にて流し込み回路形成する。That is, after drilling a reference hole and through holes 2 in an insulating substrate 1 such as a glass epoxy board or a polyimide board, a mask 4 made of photoresist 3 is formed as described above, and a conductive paste 6 is applied to this groove 5. A circuit is formed by casting using a roll coater (not shown).
あるいは、メタルマスクにて回路形成することでもよい
。但し、この方法については、版バネの影響を小さくす
るために、導電ペースト中にUV反応基を混練し、メタ
ルマスクをガイドに回路形成し、紫外線照射にて導電ペ
ーストを半硬化状態となしたのちメタルマスクを外すこ
とが好ましい。Alternatively, the circuit may be formed using a metal mask. However, in this method, in order to reduce the influence of the plate spring, a UV reactive group was kneaded into the conductive paste, a circuit was formed using a metal mask as a guide, and the conductive paste was semi-cured by UV irradiation. It is preferable to remove the metal mask afterwards.
片面処理後、反対面も同様に回路形成し、この過程にて
、スルーホールも同様に形成されることを特徴とする。After processing one side, circuits are formed on the opposite side in the same way, and through holes are similarly formed in this process.
なお、前述の回路溝7に導電ペースト6を溝環めするに
際し、スキージ又はロールコータ−(図示せず)の方向
と直交するパターンについてはボイドが生じ易い(第2
図)。そこで、ロールコータ−の方向をできるだけ回路
溝7の方向と平行にさせることが好ましい(第3図及び
第4図参照)。Note that when fitting the conductive paste 6 into the circuit groove 7 described above, voids are likely to occur in the pattern perpendicular to the direction of the squeegee or roll coater (not shown) (second
figure). Therefore, it is preferable to make the direction of the roll coater as parallel to the direction of the circuit groove 7 as possible (see FIGS. 3 and 4).
本発明方法の奏する効果は次の如くである。The effects of the method of the present invention are as follows.
(イ)印刷回数を最小限にして、回路形成が可能である
。(b) It is possible to form a circuit by minimizing the number of times of printing.
(ロ)層間絶縁がベース材であることがら膜厚変動、ボ
イド等がなく、電気特性が安定している。(b) Since the interlayer insulation is a base material, there are no film thickness fluctuations, voids, etc., and the electrical characteristics are stable.
(ハ)フラツトな面に導電回路を形成することで、回路
膜厚が安定できる。(c) By forming a conductive circuit on a flat surface, the circuit film thickness can be stabilized.
(ニ)印刷により回路形成をすることで、回路形成が容
易である。(d) By forming the circuit by printing, it is easy to form the circuit.
(ホ)マスクがメツシュスクリーンでないために、ファ
インパターンへの追従性が良好である。(e) Since the mask is not a mesh screen, it has good followability to fine patterns.
(へ)スルーホールは両面回路形成と同時に成形できる
。(f) Through-holes can be formed at the same time as double-sided circuit formation.
第1図は本発明の一実施例における製造工程説明図であ
り、
第2図、第3図及び第4図は、それぞれ、同じく、本発
明の一実施例における導電ペーストによる回路導体の形
成工程を示す説明略図であり、さらに、第5図は従来の
一例を示す製造工程説明図である。
1・・・絶縁基板(ベース材)
2・・・基準孔及びスルーホール
3・・・フォトレジスト 4・・・マスク5・・・溝
6・・・導電ペースト7・・・回路溝
特許出願人 古河電気工業株式会社
第1図
笛!
第2図
第3図
第4図
; M
2シJ 曳
)凶FIG. 1 is an explanatory diagram of the manufacturing process in one embodiment of the present invention, and FIGS. 2, 3, and 4 are respectively diagrams showing the process of forming a circuit conductor using conductive paste in one embodiment of the present invention. FIG. 5 is an explanatory diagram showing a conventional example of the manufacturing process. 1... Insulating substrate (base material) 2... Reference hole and through hole 3... Photoresist 4... Mask 5... Groove 6... Conductive paste 7... Circuit groove Patent applicant Furukawa Electric Co., Ltd. Figure 1 whistle! Figure 2 Figure 3 Figure 4;
Claims (1)
縁基板上に印刷にて形成する印刷回路基板の製造方法に
おいて、 絶縁基板に予め所定の基準孔及び/又はス ルーホールの孔あけ加工を行ない、少なくともこの基板
の片面上に回路形成用の感光性レジストをかけ、これを
所定のマスクを通して露光し現像して、所定のパターン
の回路溝を形成し、該回路溝に直かに導電ペーストを流
し込んで、導電ペーストにより所望パターンの回路導体
を絶縁基板上に印刷にて形成することを特徴とする印刷
回路基板の製造方法。[Claims] 1. A method for manufacturing a printed circuit board in which a circuit conductor in a desired pattern is formed by printing on an insulating substrate using conductive paste, the method comprising: forming predetermined reference holes and/or through holes in the insulating substrate in advance; After drilling, a photosensitive resist for circuit formation is applied on at least one side of the substrate, and this is exposed and developed through a prescribed mask to form a circuit groove in a prescribed pattern, and a photosensitive resist for forming a circuit is applied directly to the circuit groove. 1. A method for manufacturing a printed circuit board, comprising: pouring a conductive paste into the insulating substrate, and printing a circuit conductor in a desired pattern using the conductive paste on an insulating substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23011986A JPS6386496A (en) | 1986-09-30 | 1986-09-30 | Manufacture of printed circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP23011986A JPS6386496A (en) | 1986-09-30 | 1986-09-30 | Manufacture of printed circuit board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6386496A true JPS6386496A (en) | 1988-04-16 |
Family
ID=16902866
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP23011986A Pending JPS6386496A (en) | 1986-09-30 | 1986-09-30 | Manufacture of printed circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6386496A (en) |
-
1986
- 1986-09-30 JP JP23011986A patent/JPS6386496A/en active Pending
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