JP2003298208A - Manufacturing method of circuit board - Google Patents
Manufacturing method of circuit boardInfo
- Publication number
- JP2003298208A JP2003298208A JP2002103256A JP2002103256A JP2003298208A JP 2003298208 A JP2003298208 A JP 2003298208A JP 2002103256 A JP2002103256 A JP 2002103256A JP 2002103256 A JP2002103256 A JP 2002103256A JP 2003298208 A JP2003298208 A JP 2003298208A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- base material
- conductor layer
- manufacturing
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は回路基板の製造法に
関し、特には、高密度な配線パターンを形成可能な回路
基板の製造法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a circuit board, and more particularly to a method of manufacturing a circuit board capable of forming a high-density wiring pattern.
【0002】[0002]
【従来の技術とその問題点】近年、電子機器の小型化と
高機能化は益々促進されてきており、そのために回路基
板にも、高密度実装に対応するため、配線パターンの狭
ピッチ化の要求が高まってきている。2. Description of the Related Art In recent years, miniaturization and higher functionality of electronic devices have been increasingly promoted. Therefore, in order to support high-density mounting on circuit boards, it is necessary to reduce the pitch of wiring patterns. The demand is increasing.
【0003】これに対して、従来の回路基板は、導体層
に対してエッチング処理を施すことにより、配線パター
ンを形成していた。この方法を用いて製造された回路基
板の配線ピッチは導体厚み10μmでピッチ50μm程度が限
界であった。さらに狭ピッチな回路基板を製造するため
にはシード層上にめっきレジストをパターニングし、め
っきで配線を形成するセミアディティブ法を用いなけれ
ばならず、大きな設備投資が必要になるという問題があ
った。On the other hand, in the conventional circuit board, the wiring pattern is formed by etching the conductor layer. The wiring pitch of the circuit board manufactured by using this method is limited to a conductor thickness of 10 μm and a pitch of about 50 μm. In order to manufacture a circuit board with a narrower pitch, a semi-additive method of patterning a plating resist on the seed layer and forming wiring by plating must be used, which requires a large capital investment. .
【0004】[0004]
【課題を解決するための手段】本発明は、上記従来例の
問題を好適に解決するための方法を提供するものであっ
て、絶縁べース材の一方の面の導体層に配線パターンと
なる形状の溝を形成し、該溝を形成した前記導体層をマ
スク層として前記絶縁ベース材にレーザー加工、プラズ
マエッチング手法又はウエットエッチング手法を用いて
薄膜加工して溝を形成し、この溝に導電ペースト又は導
電インキを充填して配線パターンを形成することを特徴
とする回路基板の製造法が採用される。SUMMARY OF THE INVENTION The present invention provides a method for suitably solving the above-mentioned problems of the conventional example, in which a wiring pattern is formed on a conductor layer on one surface of an insulating base material. Forming a groove having the following shape, and using the conductor layer in which the groove is formed as a mask layer, the insulating base material is subjected to thin film processing by laser processing, a plasma etching method or a wet etching method to form a groove, and A method of manufacturing a circuit board, which is characterized by filling a conductive paste or a conductive ink to form a wiring pattern is adopted.
【0005】[0005]
【発明の実施の形態】以下、図示の実施例を参照しなが
ら本発明をさらに説明する。図1は、本発明の一実施例
による可撓性回路基板の製造工程図である。先ず、同図
(1)のように片面銅張り板等の如き絶縁べース材2の
一方面に導体層1を有する材料を用意する。BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be further described below with reference to the illustrated embodiments. FIG. 1 is a manufacturing process diagram of a flexible circuit board according to an embodiment of the present invention. First, as shown in FIG. 1A, a material having a conductor layer 1 on one surface of an insulating base material 2, such as a single-sided copper clad plate, is prepared.
【0006】そこで、同図(2)に示すように導体層1
をエッチングにより加工し、配線パターンの形状となる
溝3を形成する。次に、同図(3)に示すように溝3を
形成した導体層1をマスク層として絶縁ベース材2にレ
ーザー加工、プラズマエッチング手法、ウエットエッチ
ング手法で薄膜加工を行い、導電ペースト又は導電イン
キを充填する為の溝4を形成する。Therefore, as shown in FIG.
Are processed by etching to form the groove 3 having the shape of the wiring pattern. Next, the insulating base material 2 is subjected to thin film processing by laser processing, plasma etching method, or wet etching method using the conductor layer 1 having the grooves 3 as a mask layer as shown in FIG. Forming a groove 4 for filling
【0007】その後、同図(4)に示すように、形成さ
れた溝4に導電ペースト又は導電インキからなる導電性
部材5を充填する。次いで、同図(5)に示すように選
択的に導電ペースト又は導電インキからなる導電性部材
5をエッチングして配線パターン6を形成する。Thereafter, as shown in FIG. 4 (4), the formed groove 4 is filled with a conductive member 5 made of a conductive paste or conductive ink. Then, as shown in FIG. 5 (5), the conductive member 5 made of conductive paste or conductive ink is selectively etched to form the wiring pattern 6.
【0008】例えば、導体層1が銅箔であって、充填さ
れた導電性部材5に銅ペーストを用いる場合において
も、銅ペーストのほうが銅箔にくらべエッチング速度が
著しく速いため、選択的に銅ペーストをエッチング加工
することができる。ただし、このとき用いる銅ペースト
は銅粒子の充填率が高く、バインダーとなる樹脂が少な
いほうが良い。好ましくは銅粒子の充填率90%以上の銅
ペーストであれば、塩化銅、塩化鉄等の従来用いられて
いる銅のエッチング液で選択的にエッチング可能であ
る。For example, when the conductor layer 1 is a copper foil and a copper paste is used for the filled conductive member 5, the etching rate of the copper paste is significantly higher than that of the copper foil, so that the copper is selectively removed. The paste can be etched. However, it is preferable that the copper paste used at this time has a high packing rate of copper particles and a small amount of resin serving as a binder. Preferably, a copper paste having a filling rate of copper particles of 90% or more can be selectively etched with a conventionally used copper etching solution such as copper chloride or iron chloride.
【0009】なお、エッチングの選択性に乏しい組み合
わせの場合には溝加工後にマスク層となる導体層上にレ
ジスト層を形成しておくことにより、導電ペースト、導
電インキのみを選択的にエッチングできる。この場合の
レジスト層として電着レジストを用いると、レジスト層
形成時の位置合わせ工程が省略できるのみならず精度も
高く好適である。In the case of a combination having a poor etching selectivity, a conductive layer or a conductive ink alone can be selectively etched by forming a resist layer on the conductive layer serving as a mask layer after the groove processing. If an electrodeposition resist is used as the resist layer in this case, not only the alignment step at the time of forming the resist layer can be omitted, but also the accuracy is high, which is preferable.
【0010】そして、さらに導体層1に対する配線加工
を行なって他の所要の配線パターン7を形成することに
より、高密度狭ピッチな配線パターンを有する可撓性回
路基板を得ることができる。Further, by wiring the conductor layer 1 to form other required wiring patterns 7, it is possible to obtain a flexible circuit board having a wiring pattern of high density and narrow pitch.
【0011】図2は、両面銅張り板等の材料を用いて上
記と同様な手法を適用することにより、絶縁べース材2
の他の面にも上記と同様な配線パターン8,9を形成し
て両面可撓性回路基板を構成した例を示す。FIG. 2 shows an insulating base material 2 by applying a method similar to the above using a material such as a double-sided copper clad plate.
An example of forming a double-sided flexible circuit board by forming wiring patterns 8 and 9 similar to the above on the other surface is also shown.
【0012】[0012]
【発明の効果】本発明による回路基板は、導体層および
溝加工が施された絶縁ベース材に導電ペースト等を充填
した構造を有しており、導体間のスペースをさらに導体
層としているので、従来の回路基板の製造法では困難で
あった回路基板に於ける配線パターンの狭ピッチ化を好
適に達成できる。The circuit board according to the present invention has a structure in which a conductive layer and a grooved insulating base material are filled with a conductive paste or the like, and the space between the conductors is further used as the conductive layer. It is possible to preferably achieve the narrowing of the pitch of the wiring pattern on the circuit board, which was difficult with the conventional circuit board manufacturing method.
【図1】本発明の一実施例による可撓性回路基板の製造
工程図。FIG. 1 is a manufacturing process diagram of a flexible circuit board according to an embodiment of the present invention.
【図2】本発明の他の実施例による両面可撓性回路基板
の概念的断面図。FIG. 2 is a conceptual cross-sectional view of a double-sided flexible circuit board according to another embodiment of the present invention.
1 導体層 2 絶縁べース材 3 溝 4 溝 5 導電性部材 6 配線パターン 7 配線パターン 1 conductor layer 2 Insulating base material 3 grooves 4 grooves 5 Conductive member 6 wiring patterns 7 wiring pattern
Claims (2)
ターンとなる形状の溝を形成し、該溝を形成した前記導
体層をマスク層として前記絶縁ベース材にレーザー加
工、プラズマエッチング手法又はウエットエッチング手
法を用いて薄膜加工して溝を形成し、この溝に導電ペー
スト又は導電インキからなる導電性部材を充填して配線
パターンを形成することを特徴とする回路基板の製造
法。1. A groove having a shape to be a wiring pattern is formed on a conductor layer on one surface of an insulating base material, and the conductor layer having the groove is used as a mask layer to perform laser processing on the insulating base material and plasma. A method for manufacturing a circuit board, characterized in that a groove is formed by thin film processing using an etching method or a wet etching method, and a conductive pattern made of a conductive paste or conductive ink is filled in the groove to form a wiring pattern. .
ターンを形成した請求項1の回路基板の製造法。2. The method for manufacturing a circuit board according to claim 1, wherein the wiring pattern is formed on the other surface of the insulating base material.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002103256A JP2003298208A (en) | 2002-04-05 | 2002-04-05 | Manufacturing method of circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002103256A JP2003298208A (en) | 2002-04-05 | 2002-04-05 | Manufacturing method of circuit board |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2003298208A true JP2003298208A (en) | 2003-10-17 |
Family
ID=29389195
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2002103256A Pending JP2003298208A (en) | 2002-04-05 | 2002-04-05 | Manufacturing method of circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2003298208A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101063041B1 (en) * | 2009-06-29 | 2011-09-07 | 주식회사 티넷 | Microcircuit Film Substrate and Manufacturing Method |
CN112867270A (en) * | 2021-02-02 | 2021-05-28 | 沪士电子股份有限公司 | Method for printing high-speed circuit board by using conductive paste and high-speed circuit board |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07240568A (en) * | 1994-02-28 | 1995-09-12 | Mitsubishi Electric Corp | Circuit board and its manufacture |
JPH11103171A (en) * | 1997-07-28 | 1999-04-13 | Hitachi Ltd | Wiring board and its manufacture as well as electroless plating method |
JP2000003741A (en) * | 1998-06-12 | 2000-01-07 | Jsr Corp | Connector and circuit board inspecting device using the same |
JP2001352146A (en) * | 2000-06-06 | 2001-12-21 | Mitsui Chemicals Inc | Circuit substrate and method for manufacturing the same |
-
2002
- 2002-04-05 JP JP2002103256A patent/JP2003298208A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07240568A (en) * | 1994-02-28 | 1995-09-12 | Mitsubishi Electric Corp | Circuit board and its manufacture |
JPH11103171A (en) * | 1997-07-28 | 1999-04-13 | Hitachi Ltd | Wiring board and its manufacture as well as electroless plating method |
JP2000003741A (en) * | 1998-06-12 | 2000-01-07 | Jsr Corp | Connector and circuit board inspecting device using the same |
JP2001352146A (en) * | 2000-06-06 | 2001-12-21 | Mitsui Chemicals Inc | Circuit substrate and method for manufacturing the same |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101063041B1 (en) * | 2009-06-29 | 2011-09-07 | 주식회사 티넷 | Microcircuit Film Substrate and Manufacturing Method |
CN112867270A (en) * | 2021-02-02 | 2021-05-28 | 沪士电子股份有限公司 | Method for printing high-speed circuit board by using conductive paste and high-speed circuit board |
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