JPS6381841A - High-frequency integrated circuit - Google Patents

Abstract

PURPOSE:To facilitate the realization of a multistage cascade connection by a method wherein an input signal terminal and output signal terminal are connected through the intermediary of DC blocking capacitors, respectively, to an auxiliary input signal terminal and auxiliary output signal terminal. CONSTITUTION:An auxiliary input signal terminal 40 and auxiliary output signal terminal 50 are provided, are connected to an input signal terminal 4 and output signal terminal 5, respectively, through DC blocking capacitors 3a, and are located near the input signal terminal 4 and output signal terminal 5. When MMIC amplifier chips of this design are connected in cascade, connection of signal terminals between chips are accomplished by connecting the auxiliary input signal terminal 40 and output signal terminal 5 or the auxiliary output signal terminal 50 and input signal terminal 4. In this way, DC bias may be divided between chips. Accordingly, external DC blocking capacitors, as required in a conventional MMIC amplifier cascade connection design, are not needed in this design, which facilitates the realization of a multistage cascade connection.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit configuration of a high frequency integrated circuit.

[Conventional technology]

Hereinafter, a monolithic microwave integrated circuit amplifier (MMIC amplifier) will be explained as an example of a high frequency integrated circuit.

Figure 4 is a circuit diagram showing the circuit configuration of a conventional MMIC amplifier. In Figure 0, 1 is a transistor, 2 is a resistor, and 3
4 is an input signal terminal, 5 is an output signal terminal, and 6 is a DC bias application terminal of the transistor.

Next, the operation will be explained. A signal applied to the input signal terminal 4 is amplified by the transistor 1 and taken out from the output signal terminal 5. Here, a DC bias for operating the transistor 1 is supplied from a DC bias application terminal 6, and the DC bias between the transistors is separated by a DC blocking capacitor 3.

FIG. 5 is a schematic diagram of a chip pattern showing the pattern arrangement of each terminal portion of this MMIC amplifier. MM I
The C amplifier chip is mounted in a suitable package 7, as shown in FIG. 6, and connected to input signal terminals 4. Output signal terminal5.
The DC bias application terminal 6 is used by being connected to the corresponding lead portion 41.degree.51.61 of the package 7.

[Problem that the invention seeks to solve]

Since the conventional MMIC amplifier is configured as described above, when configuring a multi-stage amplifier, an external DC blocking capacitor is used to separate the DC bias between the MMIC amplifier chips as shown in Figure 7. 31, and there was a problem that the nodes could not be simply connected in cascade.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a high-frequency integrated circuit that can easily realize multi-stage cascade connection.

[Means for solving problems]

The high frequency integrated circuit according to the present invention has a conventional input.

In addition to the input and output signal terminals, an auxiliary input and an auxiliary output signal terminal are connected to the input and output signal terminals, respectively, via DC/DC capacitors.

[Function] In this invention, since the auxiliary input or auxiliary output signal terminal is connected to the output or input signal terminal of the cascade-connected circuit, the auxiliary input or auxiliary output signal terminal is connected to the output or input signal terminal of the cascade-connected circuit. It is possible to eliminate the need for a DC blocking capacitor.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an MM IC amplifier which is a high frequency integrated circuit according to an embodiment of the present invention, and FIG. 2 is a schematic diagram of a chip pattern of the circuit shown in FIG.

In both figures, 1 to 6 indicate the same as the conventional example, and 40
is an auxiliary input signal terminal, 50 is an auxiliary output signal terminal,
Both terminals 40.50 are electrically connected to the input and output signal terminals 4.5, respectively, via the DC blocking capacitor 3a, and are installed close to the input and output signal terminals 4.5.

In the MMI C amplifier with such a configuration, the MMI
When C amplifier chips are connected in series, the signal terminal connections between the chips are connected to the auxiliary input signal terminal 40, the output signal terminal 5,
Alternatively, by using the auxiliary output signal terminal 50 and the input signal terminal 4, DC bias separation between chips can be achieved. Therefore, there is no need for an external DC blocking capacitor, which was necessary in the conventional cascade connection of MMIC amplifiers, and the cascade connection can be easily performed.

Although the above embodiment has been described with reference to an MMIC amplifier, the invention is not limited to this, and it goes without saying that similar effects can be achieved even when applied to other high frequency integrated circuits.

〔Effect of the invention〕

As described above, according to the high frequency integrated circuit of the present invention, since the auxiliary input and auxiliary output signal terminals are connected to the input and output signal terminals via DC blocking capacitors, respectively, the multistage circuit of the circuit is This has the effect of making cascade connections easier.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a high frequency integrated circuit according to an embodiment of the present invention, FIG. 2 is a schematic diagram showing a chip pattern of the above embodiment, and FIG. 3 is a schematic diagram showing the state in which the above embodiments are connected in cascade. , FIG. 4 is a circuit diagram showing a conventional high-frequency integrated circuit,
FIG. 5 is a schematic diagram showing the chip pattern of the above conventional example, FIG. 6 is a diagram showing the state in which the above conventional example is incorporated into a puff cage, and FIG. 7 is a schematic diagram showing the state in which the above embodiments are connected in cascade. . In the figure, ■ is a transistor, 2 is a resistor, 3°3a is a DC blocking capacitor, 4 is an input signal terminal, 5 is an output signal terminal, 6 is a DC bias application terminal, 7 is a package,
31 is an external DC blocking capacitor, 40 is an auxiliary input signal terminal, 50 is an auxiliary output signal terminal, 41 is an input lead portion of the package, 51 is an output lead portion of the package, 6
1 is a bias lead portion of the package. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) In a high frequency integrated circuit, a circuit comprising an auxiliary input and an auxiliary output signal terminal connected to the input and output signal terminals via a DC blocking capacitor, respectively, and connecting the auxiliary input or auxiliary output signal terminals in cascade. A high-frequency integrated circuit characterized in that it is connected to an output or input signal terminal of the circuit.