JPH0320082A - Field-effect transistor and integrated circuit using same - Google Patents

Abstract

PURPOSE:To improve input/output separation of a high frequency signal, to eliminate unstability such as oscillation and to acquire stable operation by carrying out input/output of a high frequency signal to a field effect transistor(FET) in opposite positions and by providing pads which are input/output terminals to the outside in opposite positions. CONSTITUTION:Input and output of a high frequency signal to an FET 10 are performed in opposite positions. Pads 11, 13 among input/output terminal pads to the outside are provided in opposite positions for physical separation. In this case, an output matching circuit is added to a drain pad 11, an input matching circuit is added to a first gate pad 13, and a capacity is added to a terminal pad 12; then, the circuit becomes an FET amplifier. A high frequency signal is input from the pad 13 through an input matching circuit, a gate finger 10 is amplified by an FET 10a, output is taken out from the pad 11 to become an output signal through the output matching circuit. Thereby, it is possible to improve separation of input and output of a high frequency signal, to remove unstability such as oscillation and to acquire stable operation.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a field effect transistor (hereinafter abbreviated as FET) used in a high frequency band and an integrated circuit (IC) using a plurality of the field effect transistors. It is.

Conventional dual-gate FETs have a high gain in high frequency bands and a high degree of separation between each gate, so they are suitable for amplification in high frequency bands.
Widely used as a mixing element. The configuration of this dual game FET is known, for example, as described in Japanese Patent Application Laid-Open No. 146506/1983.

A conventional dual gate FET will be explained below with reference to FIG.

In Figure 3, l is the source, 2 is the drain, and 3 is the first
Gate 4 is the second gate. For example, when configuring an amplifier using this FET, the first gate 3 is normally used as the input terminal and the drain is used as the output terminal 2 to obtain desired characteristics, but the input and output are separated by distance, so the input and output are separated by distance. Separation between outputs is good.

However, in the above configuration, if a large gate width is required due to the power to be handled, the gate finger length becomes long and the gate resistance becomes high, so the NF and gain are reduced. It has deteriorated. 1. IC that implements multiple FETs
etc., it is insufficient in terms of effective utilization of the chip area.

Therefore, FET configurations in which multiple short gate fingers are used to equivalently widen the gate width have been adopted in ICs, etc., but this requires connecting multiple gates, sources, and drains. , the important issues were how to ensure input/output isolation, how to connect within the chip to suppress the occurrence of oscillation, and how to take it out to the outside.The present invention solves the above-mentioned problems of the conventional technology. , a DAIRG FET with multiple gate fingers
The purpose of this invention is to improve the degree of input/output separation of the device, eliminate instability such as oscillation, and realize stable operation of a dual-game FET and an IC using the same.

Means for Solving the Problems The present invention has a plurality of gate fingers, inputs and outputs high-frequency signals at opposing positions, and increases the physical distance between the input and output pads connected to the gate fingers. The above objective is achieved by taking measures such as providing low impedance portions between pads.

The present invention improves the input/output separation of high-frequency signals, eliminates instability such as oscillation, and operates stably.

EXAMPLE A first example of the present invention will be described below with reference to the drawings.

FIG. 1(a) is a plan view of a dual gate FET having a plurality of gate fingers according to a first embodiment of the present invention, and FIG. 1(b) is an equivalent circuit diagram.

In FIGS. 1(a) and (b), 10 is a dual-game FET with a plurality of gate fingers 10a, 11 is a drain pad, 12 is a terminal pad connecting the second gate and source, and 13 is a first gate pad. , 14 is a ground pad, 15 is a gate resistor, 16 is a source resistor, 17 is a second gate, and the intersection of the source and drain.

With the above configuration. The operation will be explained below. When an output matching circuit is added to the drain pad 1l, an input matching circuit is added to the l-th gate pad 13, and a capacitor is added to the terminal pad 12, this circuit becomes an FET amplifier. The high frequency signal is inputted from the first gate pad 13 via an input matching circuit (not shown), is amplified by the D air gate FETIO having a plurality of gate fingers 10a, and the output is taken out from the drain pad 1l. and becomes an output signal via an output matching circuit (not shown). In this configuration, there is an intersection 17 between the second gate, the source, and the drain, but since a high-frequency grounding capacitor is added externally to the second gate and the source, the impedance is low and there is no effect on the output signal. few. Therefore, in this configuration, the input and output of high-frequency signals do not cross or come close to each other, so the degree of separation between the input and output is high, and instability such as oscillation can be eliminated, and the FET is stable. Good inherent input/output separation characteristics can be obtained.

As is clear from the above description, according to this embodiment, high frequency signals are inputted and outputted to the dual game FET at opposing positions, and one of the pads which is an input/output terminal to the outside is input/output. By arranging the pads 11 and 13 at opposing positions with a physical distance between them, the degree of separation between input and output of high-frequency signals is increased, and instability such as oscillation is removed, resulting in stable operation and desired elegance. be able to.

Next, a second embodiment of the present invention will be described.

FIG. 2 is a plan view of a dual gate FET with a plurality of gate fingers in a second embodiment of the present invention. The configuration in FIG. 2 is also the same as the equivalent circuit diagram shown in FIG. In FIG. 2, the difference from the configuration in FIG. 1 is that the drain pad 11a is replaced with the l-th gate pad 13.
However, these points are not in opposing positions, but in the same direction. Components with the same numbers as in FIG. 1 have the same functions as in FIG.

The operation of the above configuration will be explained below. F
In order to input and output high-frequency signals to and from the ET at opposing positions, and to ensure input and output separation even if the pads serving as input and output terminals to the outside are in the same direction, a low impedance section (in this example) is installed between them. This is dealt with by providing a ground pad 14).

As described above, according to this embodiment, even if the pads serving as external input/output terminals are oriented in the same direction, input/output separation can be ensured, stable operation and desired characteristics can be obtained, and the position of the input/output pads can be It is possible to increase the degree of freedom in design without being subject to restrictions.

In addition, in the above embodiment, a single dual gate FET with a plurality of gate fingers 10a was described, but the same cannot be said for an IC with a plurality of gate fingers 10a, and in the case of an IC, Furthermore, it is also effective to provide a ground portion to separate a plurality of high frequency signals.

Effects of the Invention As described above, the present invention provides a dual-game FET having a plurality of gate fingers or an integrated circuit using a plurality of such FETs, in which high-frequency signals are input and output to the FET at opposing positions. In addition, by placing pads that are input/output terminals to the outside in opposing positions, increasing the physical distance between input/output pads, and providing low impedance parts between input/output pads, high-frequency signals can be It is possible to improve the degree of input/output separation, eliminate instability such as oscillation, and realize a dual-game FET that operates stably and an integrated circuit using the same, which has great industrial effects.

[Brief explanation of the drawing]

FIG. 1(a) is a plan view showing a dual-gauge FET circuit with a plurality of gate fingers according to the first embodiment of the present invention, FIG. 1(6) is an equivalent circuit diagram, and FIG. FIG. 3 is a plan view showing a dual-game FET circuit having a plurality of gate fingers in another embodiment, and FIG. 3 is a plan view showing a conventional dual-game FET. 10...Dual game with multiple gate fingers}
FET, 11...Drain pad, 12...Terminal pad, 13...First gate pad, 14...Ground pad, l5...Gate resistor, 16...Base resistor, 17... intersection. 1st base to)

Claims (4)

[Claims] (1) A field-effect transistor that has a plurality of gate fingers and has a high-frequency signal input/output section located at a position opposite to its own circuit. (2) A field-effect transistor that has a plurality of gate fingers and has a high-frequency signal input/output pad located at a position opposite to its own circuit. (3) The field effect transistor according to claim 2, further comprising a high-frequency low impedance portion provided between the high-frequency signal input/output pads. (4) An integrated circuit comprising a plurality of field effect transistors according to claim 1, or 2 or 3, to increase the degree of separation of input and output high frequency signals.