JPS60140744A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS60140744A
JPS60140744A JP58245125A JP24512583A JPS60140744A JP S60140744 A JPS60140744 A JP S60140744A JP 58245125 A JP58245125 A JP 58245125A JP 24512583 A JP24512583 A JP 24512583A JP S60140744 A JPS60140744 A JP S60140744A
Authority
JP
Japan
Prior art keywords
fets
source
common
resistor
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58245125A
Other languages
Japanese (ja)
Other versions
JPH0525181B2 (en
Inventor
Shutaro Nanbu
修太郎 南部
Masahiro Nishiuma
西馬　正博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP58245125A priority Critical patent/JPS60140744A/en
Publication of JPS60140744A publication Critical patent/JPS60140744A/en
Publication of JPH0525181B2 publication Critical patent/JPH0525181B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

PURPOSE:To obtain excellent high-frequency characteristics of the titled device by a simple constitution by connecting a plurality of FETs through a bonding wire used for a peaking coil when the FETs are cascade-connected. CONSTITUTION:A source in three cascade-connected FETs is made common, the self-bias of the three FETs is executed by one resistor R4, and a common source terminal is connected to ground potential by using a bypass capacitor C4. When the source is connected in common at that time, it is particularly important on a high-frequency circuit that ground inductance is inhibited to a small value. Consequently, a common source 40 is constituted by a conductor in not less than 1mm. width, and three FETs are loaded on the source. These source and FETs are received in a plastic package 41, a plurality of rubber conductors 42 projecting from an electric equipment pattern are faced to these FETs, and the rubber conductors 42 are connected by bonding wires 45 used for a peaking coil. The self-bias of the three FETs is executed by one resistor R4 adjoined to the common source 40, and the source 40 is connected to ground potential by using the bypass capacitor C4.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は半導体集積回路装置に関する。[Detailed description of the invention] (Industrial application field) The present invention relates to a semiconductor integrated circuit device.

（従来例の構成とその問題点） 近年ＧａＡｓＩＣによりＵＨＦ帯、ＶＨＦ帯をカバーす
るモノリシック、広帯域増幅器が開発されている。(Configuration of conventional example and its problems) In recent years, monolithic broadband amplifiers covering the UHF band and VHF band have been developed using GaAs IC.

第１図に示すのはＧａＡｓ　ＦＥＴ　負帰還広帯域増幅
器ＩＣの一例である。直流カット用コンデンサＣｆ帰還
抵抗ＲｆおよびＦＥＴのａｍ？：最適に設計することに
より３０〜２０００　ＭＴ（ｚの広帯域でＮＦ　＝　２
．０　ｄＢという性能が得られている。利得をさらに太
きくする目的で第１図の広帯域増幅器を多段に接続した
第２図に示すような増幅器も開発されている。FIG. 1 shows an example of a GaAs FET negative feedback wideband amplifier IC. DC cut capacitor Cf feedback resistor Rf and FET am? :30-2000 MT (NF = 2 in wide band of z) by optimal design
．． A performance of 0 dB was obtained. In order to further increase the gain, an amplifier as shown in FIG. 2 has also been developed in which the broadband amplifiers shown in FIG. 1 are connected in multiple stages.

ところで第１図、第２図においてＧａＡｓ基板上にモノ
リシ、り化されているのは、点線で囲まれた部分のみで
あり、チョーク・コイルＬ１〜Ｌ３、バイパス用コンデ
ンサＣ１〜Ｃ３、および自己バイアス用抵抗Ｒ，−Ｒ３
はチノフ０の外に伺加して構成している。自己バイアス
用抵抗Ｒ，％Ｒ３のモノリシック化は比較的容易である
が、チョーク・コイルやバイパス用コンデンサは値が大
きくモノリシ、り化は困難であり、そのため、チョーク
・コイル、パイノぐス用コンデンサＩｄ■Ｃｆ、ｆの外
付けとする方がコスト上有利である。By the way, in Figures 1 and 2, only the parts surrounded by dotted lines are monolithically formed on the GaAs substrate, including choke coils L1 to L3, bypass capacitors C1 to C3, and self-bias. Resistor R, -R3
is composed of additions outside of Chinov 0. It is relatively easy to make the self-bias resistors R and %R3 monolithic, but choke coils and bypass capacitors have large values and are difficult to make monolithic. It is more advantageous in terms of cost to externally attach Id■Cf and f.

ところで、一般に高周波回路では寄生の容量やインダク
タンスの影響で高周波特性の低下をまねく。このため、
できる限り寄生容量やインダクタンスの発生を抑えるこ
とが必要であるが、その他に第３図に示すように、段間
にピーキングコイル３１と称するインダクタンスを挿入
して高周波特性の低下を補償する方法が行われている。By the way, in high frequency circuits, the high frequency characteristics generally deteriorate due to the influence of parasitic capacitance and inductance. For this reason,
It is necessary to suppress the generation of parasitic capacitance and inductance as much as possible, but there is also a method of inserting an inductance called a peaking coil 31 between stages to compensate for the deterioration of high frequency characteristics, as shown in Figure 3. It is being said.

々ころが５０〜２０００ＭＴ（ｚｆ！ｉｊ度の周波数で
はこのピーキングコイル３１のインダクタンスとして、
０５〜数ｎＨの値が必要であり、このコイルをモノリ／
、りしようとすると太き々面積をチップ上で占でし件う
ことに々り不利であった。The inductance of this peaking coil 31 at a frequency of 50 to 2000 MT (zf!ij degrees) is
A value of 0.05~several nH is required, and this coil can be used as a monolith/
If you tried to do this, you would be at a huge disadvantage because you would have to guess the area on the chip.

（発明の目的） 本発明は、以上の問題点を解決する、ピーキングコイル
が簡単かつ効果的に接続された半導体集積回路装置を提
供するものである。(Object of the Invention) The present invention solves the above problems and provides a semiconductor integrated circuit device in which a peaking coil is simply and effectively connected.

（発明の構成） この目的を達成するために、本発明の半導体集積回路装
置は、複数の電界効果トランジスタがピーキングコイル
用としてのボンディングワイヤを介して多段に縦続接続
されていることを特徴とするもので、これにより簡単な
構成で優れた高周波特性が得られる。(Structure of the Invention) In order to achieve this object, the semiconductor integrated circuit device of the present invention is characterized in that a plurality of field effect transistors are cascade-connected in multiple stages via bonding wires for peaking coils. This allows excellent high-frequency characteristics to be obtained with a simple configuration.

（実施例の説明） 本発明を第３図に示す広帯域３段アンプの実施例に基づ
いて説明する。(Description of Embodiments) The present invention will be described based on an embodiment of a wideband three-stage amplifier shown in FIG.

第３図に示すように、この実施例は縦続接続されだ３つ
のＦＥＴのソースを共通にし、この３つのＦＥＴの自己
バイアスをひとつの抵抗Ｒ４で行なうようにしたもので
ある。Ｃ４は共通ソース端子を接地電位に落すだめのパ
イ・ぐスコンデンサである。As shown in FIG. 3, in this embodiment, three cascade-connected FETs have a common source, and the self-biasing of these three FETs is performed by one resistor R4. C4 is a pi-gas capacitor for dropping the common source terminal to ground potential.

ところでソースを共通接続する際、その接地インダクタ
ンスを小さく抑えることが、高周波回路の場合特に重要
である。そこで、本実施例では第４図の実装図のように
、共通ソース４０を幅が１ｍｍ以上の導体で構成した。By the way, when connecting sources in common, it is especially important for high frequency circuits to keep the ground inductance low. Therefore, in this embodiment, as shown in the implementation diagram of FIG. 4, the common source 40 is constructed of a conductor having a width of 1 mm or more.

第４図で４１はプラスチック・ぐ、ターンであり、７Ｉ
２はコム導体、斜線部は導体実装・ぐターン、４３はケ
゛〜トを接地電位に落す抵抗Ｒである。４４は第３図の
点線で囲１れた部分が、モノリン、り化されたＧａＡｓ
ＩＣチ。In Figure 4, 41 is a plastic turn, and 7I
2 is a comb conductor, the shaded area is a conductor mounting circuit, and 43 is a resistor R that lowers the case to the ground potential. 44, the part surrounded by the dotted line in Fig. 3 is monophosphorized GaAs.
IC Chi.

プである。第４図では一段アンノが構成されたテップを
３チツプ用いている。It is a pool. In Fig. 4, three chips each having a single-stage antenna are used.

本発明は第４図に示すように、ボンディングワイヤ４５
で股間を接続し、これを−一キングコイルとした点に特
徴かある。もちろん３ナノｆをＩチップにまとめて、】
チノゾ上で同様に段間をボンディングワイヤで配線して
も良い。As shown in FIG. 4, the present invention has a bonding wire 45
It is unique in that the crotch is connected with the crotch, and this is made into a -1 King coil. Of course, 3 nano fs are combined into an I chip,]
Similarly, bonding wires may be used to wire between the stages on the chinozo.

本実施例ではＣ４はｌｏｏｏｐＦ以上、Ｒ４は１０、Ｑ
、Ｒは１にΩ以上で構成した。−！た、段間のピーキン
グコイル用のワイヤの長さハ２Ｉｌｌ＋ｌ＋（２０μｍ
φ）とした。これはほぼ２　ｎＨのインダクタンスを与
える。In this example, C4 is loopopF or more, R4 is 10, and Q
, R was configured to be 1Ω or more. -! In addition, the length of the wire for the peaking coil between stages is 2Ill+l+(20μm
φ). This gives an inductance of approximately 2 nH.

このアンプは３０〜２０００　Ｍ）Ｔｚという広帯域で
３３〜２８　ｄＢの利得、２．２ｄＢ　以下のＮＦが得
られたＯ なお、本実施例では抵抗Ｒ４、Ｒは外付けとしだが、こ
れらの抵抗Ｒ４，Ｒをモノリンツク化してもよい。第５
図はケ゛−ト接地用抵抗Ｒをモノリン、りに集積化した
アンプを用いた本発明の他の実施例である。また、３つ
のＦＥＴをすべてＶＯ２”ＱＶで動作させる場合には、
Ｒ４＋　Ｃ４を取除き、共通ソース５１をそのまま接地
すればよい。This amplifier achieved a gain of 33 to 28 dB and an NF of 2.2 dB or less over a wide band of 30 to 2000 M)Tz.In this example, resistors R4 and R are externally attached, but these resistors R4 , R may be monolinked. Fifth
The figure shows another embodiment of the present invention using an amplifier in which the gate grounding resistor R is integrated into a monolithic structure. Also, when operating all three FETs at VO2''QV,
R4+C4 may be removed and the common source 51 may be grounded as is.

（発明の効果） 以上のように、本発明による半導体集積回路装置は、複
数の電界効果トランジスタがボンディングワイヤを用い
た用いたピーキングコイルを介シて多段に縦続接続され
ており、きわめて簡単な構成で優れた高周波特性が得ら
れる。(Effects of the Invention) As described above, the semiconductor integrated circuit device according to the present invention has an extremely simple structure in which a plurality of field effect transistors are cascaded in multiple stages via peaking coils using bonding wires. Excellent high frequency characteristics can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はＧａＡｓ　ＦＥＴ負帰還増慴器■Ｃの回路図、
第２図は従来のＧａＡｓ　３段負帰還増幅器ＴＣの回路
図、第３図は本発明の一実施例によるＧａＡｓ　３段負
帰還増幅器ＩＣの回路図、第４図は本発明の一実施例に
よるｒｃ実実装パター同図第５図は本発明の他の実施例
の回路図である。 Ｒ・ケ゛−１・接地用抵抗、Ｒ１−Ｒ４自己バイアス用
抵抗、Ｃｌ−０４バイパス用コンｆ　ｙ　サ、Ｌｌ〜Ｌ
３・チョークコイル、３１・　ピーキングコイル、４０
・・共通ソース導体、４１・・・プラスチツクＩパッケ
ージ、４２・・コムノｅターフ、４３・ダート用接地抵
抗、４４・ＧａＡｓ１Ｃチツプ、４５・　ピーキング用
ボンディングワイヤ。 第１図 ＧＮＤ 第２図 第３図 第４図 ＧＮＤ 第５図Figure 1 is a circuit diagram of GaAs FET negative feedback amplifier ■C.
FIG. 2 is a circuit diagram of a conventional GaAs three-stage negative feedback amplifier TC, FIG. 3 is a circuit diagram of a GaAs three-stage negative feedback amplifier IC according to an embodiment of the present invention, and FIG. 4 is a circuit diagram according to an embodiment of the present invention. RC Actual Implementation Putter FIG. 5 is a circuit diagram of another embodiment of the present invention. R・Key-1・Grounding resistor, R1-R4 self-bias resistor, Cl-04 bypass capacitor, Ll~L
3. Choke coil, 31. Peaking coil, 40
・・Common source conductor, 41・Plastic I package, 42・Comno e Turf, 43・Grounding resistor for dirt, 44・GaAs1C chip, 45・Bonding wire for peaking. Figure 1 GND Figure 2 Figure 3 Figure 4 GND Figure 5

Claims (1)

【特許請求の範囲】[Claims] 複数の電界効果トランジスタがピーキングコイル用とし
てのボンディングワイヤを介して多段に縦続接続されて
いることを特徴とする半導体集積回路装置。A semiconductor integrated circuit device characterized in that a plurality of field effect transistors are cascaded in multiple stages via bonding wires for peaking coils.
JP58245125A 1983-12-28 1983-12-28 Semiconductor integrated circuit device Granted JPS60140744A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58245125A JPS60140744A (en) 1983-12-28 1983-12-28 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58245125A JPS60140744A (en) 1983-12-28 1983-12-28 Semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPS60140744A true JPS60140744A (en) 1985-07-25
JPH0525181B2 JPH0525181B2 (en) 1993-04-12

Family

ID=17128992

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58245125A Granted JPS60140744A (en) 1983-12-28 1983-12-28 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS60140744A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5128227A (en) * 1990-03-27 1992-07-07 Agfa-Gevaert, N.V. Electrophotographic recording material having a julolidine hydrazone compound
JP2011019047A (en) * 2009-07-08 2011-01-27 Mitsubishi Electric Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5128227A (en) * 1990-03-27 1992-07-07 Agfa-Gevaert, N.V. Electrophotographic recording material having a julolidine hydrazone compound
JP2011019047A (en) * 2009-07-08 2011-01-27 Mitsubishi Electric Corp Semiconductor device

Also Published As

Publication number Publication date
JPH0525181B2 (en) 1993-04-12

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