JPH0572764B2 - - Google Patents

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Publication number
JPH0572764B2
JPH0572764B2 JP57050580A JP5058082A JPH0572764B2 JP H0572764 B2 JPH0572764 B2 JP H0572764B2 JP 57050580 A JP57050580 A JP 57050580A JP 5058082 A JP5058082 A JP 5058082A JP H0572764 B2 JPH0572764 B2 JP H0572764B2
Authority
JP
Japan
Prior art keywords
amplifier
resistor
bias
fet
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57050580A
Other languages
Japanese (ja)
Other versions
JPS58168308A (en
Inventor
Kazuhiko Honjo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP5058082A priority Critical patent/JPS58168308A/en
Publication of JPS58168308A publication Critical patent/JPS58168308A/en
Publication of JPH0572764B2 publication Critical patent/JPH0572764B2/ja
Granted legal-status Critical Current

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  • Amplifiers (AREA)

Description

【発明の詳細な説明】 本発明は広帯域高効率増幅器に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a broadband high efficiency amplifier.

近年、VHF、UHF帯域移動通信、携帯電話装
置に用いる広帯域増幅器の開発が行なわれてい
る。この増幅器には、広帯域特性を有することと
同時に低消費電力であることが要求される。通常
この種の用途には、無損失回路を用いた整合増幅
器あるいは抵抗と結合コンデンサを用いた抵抗・
容量結合増幅器が用いられる。しかしながら整合
増幅器においては、集中定数キヤパシタ、インダ
クタおよび分布定数線路等の、周波数に依つてリ
アクタンスが変化する回路素子を用いるため広帯
域化が難かしく、さらに寄生発振等の不安定動作
を起こし易い。通常整合増幅器の帯域は1〜2オ
クターブが限度である。一方抵抗容量結合増幅器
では回路素子に周波数特性を持たない抵抗を用い
るため広帯域化は容易であり寄生発振等も起こり
にくい。しかしながら抵抗容量結合増幅器では直
流バイアス電流、電圧を抵抗を通じて供給するた
め、この抵抗による電力損失によつて増幅器の消
費電力が大幅に増えるという欠点がある。
In recent years, wideband amplifiers for use in VHF and UHF band mobile communications and mobile phone devices have been developed. This amplifier is required to have wideband characteristics and low power consumption. Typically, this type of application uses a matched amplifier using a lossless circuit or a resistor/coupled amplifier using a resistor and coupling capacitor.
A capacitively coupled amplifier is used. However, since matching amplifiers use circuit elements whose reactances vary depending on frequency, such as lumped constant capacitors, inductors, and distributed constant lines, it is difficult to achieve a wide band, and furthermore, unstable operation such as parasitic oscillation is likely to occur. Usually, the bandwidth of a matched amplifier is limited to one to two octaves. On the other hand, in a resistor-capacitive coupling amplifier, a resistor having no frequency characteristics is used as a circuit element, so it is easy to widen the band, and parasitic oscillations are less likely to occur. However, the resistance-capacitive coupling amplifier has the disadvantage that the DC bias current and voltage are supplied through the resistor, and the power consumption of the amplifier increases significantly due to the power loss caused by the resistor.

本発明の目的は、前記欠点を除去した広帯域高
効率増幅器を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a broadband high-efficiency amplifier that eliminates the above drawbacks.

本発明によれば、抵抗と直流阻止キヤパシタと
の直列回路を交流負荷とし、増幅帯域の最下部に
おいても前記抵抗に比べて十分に高いインピーダ
ンスをもつインンダクタを通じて、直接増幅用ト
ランジスタのドレイン電極(あるいはコレクタ電
極)に直流バイアス電流および電圧を供給するこ
とを特徴とする広帯域、高効率増幅器が得られ
る。
According to the present invention, a series circuit of a resistor and a DC blocking capacitor is used as an AC load, and the drain electrode (or A broadband, high-efficiency amplifier is obtained, which is characterized by supplying a DC bias current and voltage to the collector electrode).

このような本発明においては、交流負荷は周波
数特性を持たない抵抗となるため広帯域化と小型
化が可能で、直流バイアス供給はインダクタを通
じて行うため不要な電力損失が減るため、広帯域
高効率増幅器が実現できる。なお、本増幅器にお
いては、前記インダクタを介さずに、交流用負荷
抵抗を介して直流バイアスを供給することもでき
るため、消費電力を犠牲にして、回路動作の安定
化を計つた増幅器への転用も可能である。これら
の特徴は特に同一回路の大量生産手段であるモノ
リシツク集積化増幅器において大きな効果をも
つ。
In the present invention, since the AC load is a resistor with no frequency characteristics, it can be made wider and more compact, and the DC bias supply is performed through an inductor, which reduces unnecessary power loss, making it possible to use a wide-band, high-efficiency amplifier. realizable. In addition, in this amplifier, DC bias can be supplied through an AC load resistor instead of through the inductor, so it can be used as an amplifier that stabilizes circuit operation at the expense of power consumption. is also possible. These features are particularly effective in monolithically integrated amplifiers, which are a means of mass-producing identical circuits.

以下本発明を図面を用いて詳述する。 The present invention will be explained in detail below using the drawings.

第1図は従来例の2段構成抵抗・容量結合増幅
器を説明するための図で、aはその等価回路、b
は初段FETにとつての交流等価回路、cは初段
FETにとつての直流等価回路である。第1図a
においてソース電極3が接地された初段FETの
ドレイン電極2にはRLとCBの直列回路が並列に
接続され、このRLとCBの間にはバイアス供給端
子7が設けられている。前記ドレイン電極2と後
段FETゲート電極5の間には結合キヤパシタCC
が設けられ、該ゲート電極5には数kΩの抵抗値
をもつRGを通じてバイアス電圧が与えられる。
後段FETのソース電極6は接地されている。1
は前段FETのゲート電極、4は後段トランジス
タのドレイン電極である。RGおよびFETの入力
インピーダンスはRLより十分に高いから、初段
FETにとつての交流等価回路は第1図bのよう
になる。さらに直流等価回路は第1図cのように
なる。
Figure 1 is a diagram for explaining a conventional two-stage resistor-capacitive coupling amplifier, where a is its equivalent circuit, and b
is the AC equivalent circuit for the first stage FET, c is the first stage
This is the DC equivalent circuit for FET. Figure 1a
A series circuit of R L and C B is connected in parallel to the drain electrode 2 of the first stage FET whose source electrode 3 is grounded, and a bias supply terminal 7 is provided between R L and C B. A coupling capacitor C C is connected between the drain electrode 2 and the subsequent FET gate electrode 5.
is provided, and a bias voltage is applied to the gate electrode 5 through R G having a resistance value of several kΩ.
The source electrode 6 of the latter stage FET is grounded. 1
4 is the gate electrode of the front-stage FET, and 4 is the drain electrode of the rear-stage transistor. Since the input impedance of R G and FET is sufficiently higher than R L , the first stage
The AC equivalent circuit for FET is shown in Figure 1b. Furthermore, the DC equivalent circuit becomes as shown in Figure 1c.

第2図−cにおいて、RLで消費される電力は、
RLを流れる電流をIDとすると、RLI2Dとなる。
In Figure 2-c, the power consumed by R L is
If the current flowing through R L is I D , then R L I 2D .

第2図は本発明の一実施例であるところの
FET2段構成の広帯域・高効率増幅器を説明する
ための図である。図においてソース電極13が接
地されたFETのドレイン電極12には、RLとCB
の直列回路が並列に設けられ、さらに一端にバイ
アス供給端子を備えたインダクタLBの他端が接
続されている。前記ドレイン電極12と後段
FETゲート電極15の間には結合キヤパシタCC
が設けられ、ゲート電極15には高抵抗RGを通
じて端子18からゲートバイアス電圧が供給され
る。RLとCBの間には初段FETのドレインバイア
ス供給のための第二の端子が設けられている。1
1は初段FETのゲート電極で、14、16は
各々後段FETのドレイン電極およびソース電極
である。LB、LGおよび後段FETの入力インピー
ダンスはRLに比べて十分に高いから、第2図a
の回路の交流等価回路は、第2図bのようにな
る。また直流等価回路は第2図cのようになる。
Figure 2 shows an embodiment of the present invention.
FIG. 2 is a diagram for explaining a wideband, high-efficiency amplifier with a two-stage FET configuration. In the figure, the drain electrode 12 of the FET whose source electrode 13 is grounded has R L and C B
series circuits are provided in parallel, and the other end of an inductor L B having a bias supply terminal at one end is connected. The drain electrode 12 and the subsequent stage
A coupling capacitor C C is connected between the FET gate electrodes 15.
is provided, and a gate bias voltage is supplied to the gate electrode 15 from a terminal 18 through a high resistance RG . A second terminal for supplying drain bias to the first stage FET is provided between R L and C B. 1
1 is the gate electrode of the first stage FET, and 14 and 16 are the drain electrode and source electrode of the second stage FET, respectively. Since the input impedances of L B , L G and the subsequent FET are sufficiently high compared to R L , Fig. 2a
The AC equivalent circuit of the circuit is as shown in Fig. 2b. The DC equivalent circuit is as shown in Figure 2c.

第2図実施例の増幅器では直流バイアスをイン
ダクタを通じて供給するためFET外部では直流
電力は消費されない。したがつて本実施例の増幅
器では、初段回路だけで、従来例増幅器に比べて
I2RLだけ消費電力を減らすことがでできる。なお
本実施例増幅器には第二のバイアス供給端子19
が設けられているため、抵抗RLを通じてバイア
スを供給することも可能であり、効率を犠牲にし
て寄生発振等を起こしにくい安定な増幅器として
使用することも可能である。
In the amplifier of the embodiment shown in FIG. 2, DC bias is supplied through the inductor, so no DC power is consumed outside the FET. Therefore, in the amplifier of this example, the first stage circuit alone has a lower power consumption than the conventional amplifier.
It is possible to reduce power consumption by I 2 R L. Note that the amplifier of this embodiment has a second bias supply terminal 19.
, it is possible to supply bias through the resistor R L , and it is also possible to use it as a stable amplifier that is less likely to cause parasitic oscillations at the expense of efficiency.

第3図は第2図実施例増幅器をモノリシツク化
した場合の回路構成図である。図において構成要
素11から19までは、第2図と同一構成要素で
あり同一記号をもつて示している。RG、CC、CB
も第2図と同じものを示す。21はキヤパシタ
CBのアース用ボンデイングパツド、22はキヤ
パシタCCの下部電極、23は誘電体フイルムで
ある。図中斜線部はイオン注入により形成された
n型チヤンネル、24は半絶縁性GaAs基板であ
る。12,13,14,16,22,25はオー
ミツクメタル、11,15はシヨツトキーメタル
から成る。第3図実施例増幅器では外部インダク
タLBを12に接続して、LBを通じてドレインバ
バイアスを供給し、低消費電力化が計れる。また
19に直流電圧を加えて抵抗RLを介してドレイ
ンバイアスを供給することも可能で、消費電力を
犠牲にして高安定化を計ることもできる。第3図
回路はこれらの機能が1つのモノリシツク集積回
路の中に納められている。
FIG. 3 is a circuit configuration diagram when the amplifier of the embodiment of FIG. 2 is made into a monolithic structure. In the figure, components 11 to 19 are the same components as in FIG. 2 and are indicated by the same symbols. R G , C C , C B
also shows the same thing as Figure 2. 21 is capacitor
C B is a bonding pad for grounding, 22 is a lower electrode of capacitor C C , and 23 is a dielectric film. The shaded area in the figure is an n-type channel formed by ion implantation, and 24 is a semi-insulating GaAs substrate. 12, 13, 14, 16, 22, and 25 are made of ohmic metal, and 11 and 15 are made of shot key metal. In the embodiment amplifier of FIG. 3, an external inductor L B is connected to 12, and a drain bias is supplied through L B , thereby reducing power consumption. It is also possible to supply a drain bias through the resistor R L by applying a DC voltage to 19, and it is also possible to achieve high stability at the expense of power consumption. The circuit of FIG. 3 incorporates these functions into one monolithic integrated circuit.

このような本発明によれば、交流負荷は抵抗で
直流バイアス供給はインダクタを通じて行うため
小型で広帯域で高効率の増幅器が実現できる。さ
らに本発明においては前記インンダクタを介さず
に交流負荷抵抗を通じて直流バイアスを供給する
こともできるため消費電力を犠牲にした高安定動
作増幅器への転用も可能であり、特に同一回路の
大量生産手段であるモノリシツク集積化増幅器に
おいて大きな効果をもつ。
According to the present invention, since the AC load is a resistor and the DC bias is supplied through an inductor, a compact, wideband, and highly efficient amplifier can be realized. Furthermore, in the present invention, since DC bias can be supplied through an AC load resistor without going through the inductor, it is also possible to use it as a highly stable operation amplifier at the expense of power consumption, especially when mass-producing the same circuit. This has great effect in some monolithically integrated amplifiers.

なお、第3図実施例のモノリシツク増幅器では
半導体基板としてGaAsを用いたが半導体は
GaAsに限らずSi、InP等のいずれでもよい。
Note that although GaAs was used as the semiconductor substrate in the monolithic amplifier of the embodiment shown in FIG.
It is not limited to GaAs, but may be Si, InP, etc.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来例の広帯域増幅器、第2図は本発
明の一実施例の広帯域増幅器、第3図は第2図実
施例増幅器のモノリシツク構成例である。 第1図において1,5はFETゲート電極、3,
6はソース電極、2,4はドレイン電極、7はド
レインバイアス供給端子、8はゲートバイアス供
給端子、RL、RGは抵抗、CB、CCはキヤパシタで
ある。第2図において11,15はFETゲート
電極、13,16はソース電極、12,14はド
レイン電極、17,19はバイアス供給端子、
RL、RGは抵抗、CB、CCはキヤパシタ、LBはイン
ダクタである。第3図において斜線部はn型チヤ
ンネル、24は半絶縁性GaAs基板、23は誘電
体フイルムである。
FIG. 1 shows a conventional wideband amplifier, FIG. 2 shows a wideband amplifier according to an embodiment of the present invention, and FIG. 3 shows an example of a monolithic configuration of the amplifier of the embodiment shown in FIG. In Fig. 1, 1 and 5 are FET gate electrodes, 3,
6 is a source electrode, 2 and 4 are drain electrodes, 7 is a drain bias supply terminal, 8 is a gate bias supply terminal, R L and RG are resistors, and C B and C C are capacitors. In FIG. 2, 11 and 15 are FET gate electrodes, 13 and 16 are source electrodes, 12 and 14 are drain electrodes, 17 and 19 are bias supply terminals,
R L and R G are resistors, C B and C C are capacitors, and L B is an inductor. In FIG. 3, the shaded area is an n-type channel, 24 is a semi-insulating GaAs substrate, and 23 is a dielectric film.

Claims (1)

【特許請求の範囲】[Claims] 1 抵抗と直流阻止キヤパシタとの直列回路を交
流負荷とし、増幅帯域の最下部においても前記抵
抗に比べて十分に高いインピーダンスを持つイン
ダクタを通じて直接増幅用トランジスタのドレイ
ン電極(あるいはコレクタ電極)に直流バイアス
電流および電圧を供給することを特徴とする広帯
域高効率増幅器。
1 A series circuit of a resistor and a DC blocking capacitor is used as an AC load, and a DC bias is applied directly to the drain electrode (or collector electrode) of the amplification transistor through an inductor that has a sufficiently higher impedance than the resistor even at the bottom of the amplification band. Wideband high efficiency amplifier characterized by supplying current and voltage.
JP5058082A 1982-03-29 1982-03-29 Wide-band and high-efficiency amplifier Granted JPS58168308A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5058082A JPS58168308A (en) 1982-03-29 1982-03-29 Wide-band and high-efficiency amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5058082A JPS58168308A (en) 1982-03-29 1982-03-29 Wide-band and high-efficiency amplifier

Publications (2)

Publication Number Publication Date
JPS58168308A JPS58168308A (en) 1983-10-04
JPH0572764B2 true JPH0572764B2 (en) 1993-10-13

Family

ID=12862917

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5058082A Granted JPS58168308A (en) 1982-03-29 1982-03-29 Wide-band and high-efficiency amplifier

Country Status (1)

Country Link
JP (1) JPS58168308A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009218528A (en) * 2008-03-13 2009-09-24 Furukawa Electric Co Ltd:The GaN-BASED FIELD EFFECT TRANSISTOR

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995005027A1 (en) * 1993-08-10 1995-02-16 Fujitsu Limited Low-current amplifier

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4271433A (en) * 1979-11-23 1981-06-02 Rca Corporation SAW Filter preamplifier
JPS58142609A (en) * 1982-02-17 1983-08-24 Nippon Telegr & Teleph Corp <Ntt> Low voltage driving method of fet power amplifier

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4271433A (en) * 1979-11-23 1981-06-02 Rca Corporation SAW Filter preamplifier
JPS58142609A (en) * 1982-02-17 1983-08-24 Nippon Telegr & Teleph Corp <Ntt> Low voltage driving method of fet power amplifier

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009218528A (en) * 2008-03-13 2009-09-24 Furukawa Electric Co Ltd:The GaN-BASED FIELD EFFECT TRANSISTOR

Also Published As

Publication number Publication date
JPS58168308A (en) 1983-10-04

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