JPS62188275A - Field effect transistor - Google Patents
Field effect transistorInfo
- Publication number
- JPS62188275A JPS62188275A JP61030009A JP3000986A JPS62188275A JP S62188275 A JPS62188275 A JP S62188275A JP 61030009 A JP61030009 A JP 61030009A JP 3000986 A JP3000986 A JP 3000986A JP S62188275 A JPS62188275 A JP S62188275A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- fingers
- electrode
- drain
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 239000012535 impurity Substances 0.000 claims abstract description 4
- 238000009792 diffusion process Methods 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 230000003071 parasitic effect Effects 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004026 adhesive bonding Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は電界効果１〜ランジスタに関し、特に高周波高
出力用電界効果１〜ランシスタに関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a field effect 1 to Lansistor, and particularly to a field effect 1 to Lansistor for high frequency and high output.
従来、高周波高出力用電界効果トランジスタは、第２図
に示すように、同一半導体基板上にそれぞれ必要数のド
レイン５ソース及びターｌ−電極のホンディングパッド
が用意されていた１、そしてソース接地の場合は、入力
側であるグー１〜電極用ボンディングパッド３と出力側
である１・しイン電極用ボンディングパッド１は電極の
長平方向に対してそれぞれ対向して設けられ、ソース電
極用ボンディングパ・ソド２はゲート電極用ボンティン
グパツド３かまたはドレイン電属用ボンディングバ・ソ
ド１のどちらかと同じ側に配置されているのか一般的と
なっていた。Conventionally, as shown in Fig. 2, a high frequency, high power field effect transistor has a required number of drain, source, and tar-electrode bonding pads on the same semiconductor substrate. In this case, the bonding pads 1 to 3 for electrodes on the input side and the bonding pads 1 for electrodes 1 and 1 on the output side are provided facing each other in the longitudinal direction of the electrodes, and the bonding pads for source electrodes・Generally, the pad 2 is placed on the same side as either the bonding pad 3 for the gate electrode or the bonding pad 1 for the drain metal.
〔発明が解決しようとする問題点、１
上述した従来のボンディングパッドの配置においては、
高周波入力電力か、グーｌ〜電極用ホンディンク゛バ・
ソト３を庁して複数個のケート電極のフィン力０に分岐
されるが、高周波帯においては、グー１〜電極の接続部
７やグーＩ−電極のフィンガ〔３自体のもつ抵抗分によ
る電位降下や寄生インダクタンスによる位相回転により
入力電力の減衰が起る。[Problems to be solved by the invention, 1. In the conventional bonding pad arrangement described above,
Whether it is high frequency input power, or
The fin force of the plurality of electrodes is branched to 0 by controlling Soto 3, but in the high frequency band, the potential due to the resistance of the connection part 7 of Goo 1 to the electrode and the resistance of Goo I to the electrode finger [3 itself] Attenuation of input power occurs due to phase rotation due to drop and parasitic inductance.
また、この悪影響を低減させる為にゲート電極のフィン
ガ６を短くすると、高出力化する為にはグーＩ−電極の
フィンガの本数をより増やさなければならず、そのなめ
半導体チップの横幅が不必要に大きくなり、半導体チッ
プへの各部分への入力電力の駆動の際、位相ずれを引き
起し、期待したほどの高出力化が実現できないという大
きな問題点があった。In addition, if fingers 6 of the gate electrode are shortened in order to reduce this negative effect, the number of fingers of the goo I-electrode must be increased in order to achieve high output, which makes the width of the semiconductor chip unnecessary. There was a major problem in that this caused a phase shift when driving the input power to each part of the semiconductor chip, making it impossible to achieve the high output as expected.
本発明の目的は、高出力化が可能な電界効果トランジス
タを提供することにある。An object of the present invention is to provide a field effect transistor that can achieve high output.
１、問題点を解決するための手段〕
本発明の電界効果Ｉ−ランジスタは、半導体基板上に形
成された不純物拡散層からなるソース領域とドレイン領
域と、このソース領域とドレイン領域間に形成されたゲ
ート酸化膜と、前記ソース領域とドレイン領域及びゲー
ト酸化膜−Ｌに形成されたソース電極とドレイン電極及
びゲート電極とを有する電界効果トランジスタであって
、前記ケ＝１〜電極は２個のボンデインクパットを有し
がつこの２１固の７１テンデイン・グパッ１〜はグーＪ
−電％のフィンガの長手方向の対向する位置に形成され
ているものである。1. Means for Solving the Problems] The field effect I-transistor of the present invention includes a source region and a drain region made of an impurity diffusion layer formed on a semiconductor substrate, and a region formed between the source region and the drain region. A field effect transistor having a gate oxide film formed on the source region, a drain region, and a source electrode, a drain electrode, and a gate electrode formed on the gate oxide film-L, wherein the electrodes include two electrodes. This 21 hard 71 Tenden Gupat 1 ~ is Gu J with Bonde Ink Pad
- They are formed at opposite positions in the longitudinal direction of the electric fingers.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の平面図である。FIG. 1 is a plan view of one embodiment of the present invention.
第１図において、シリコン基板上に形成された不純物拡
散層からなるドレイン領域、ソース領域上には、ドレイ
ン電極用ボンディングバ°ツド１が接続されたドレイン
電極のフィンガ４と、ソース電極用ボンディングパ・ソ
ド２が接続されたソース電極のフィンガ５がそれぞれ形
成されている。そしてソース領域とドレイン領域間のゲ
ート酸化膜−、ヒには、２つのゲート電極の接続部７Ａ
、７Ｂに接続されたゲート電極のフィンガ６が形成され
ており、このグー）〜電極の接続部７Ａ、７Ｂにはそれ
ぞれゲート電極用ボンディングパッド３Ａ、３Ｂか接続
されている。In FIG. 1, on the drain region and the source region, which are formed of an impurity diffusion layer formed on a silicon substrate, there are a finger 4 of the drain electrode to which a bonding pad 1 for the drain electrode is connected, and a bonding pad for the source electrode. - Source electrode fingers 5 to which the electrodes 2 are connected are respectively formed. The gate oxide film between the source region and the drain region has a connecting portion 7A of the two gate electrodes.
, 7B are formed, and gate electrode bonding pads 3A, 3B are connected to these electrode connecting portions 7A, 7B, respectively.
このように構成された本実施例においては、ゲート電極
相ボンディングパッド３Ａ、３Ｂからグー１〜電極のフ
ィンガ６迄の距離が、従来のゲート電極用ボンディング
パッドが１個の場合に比べて、実効的に短くなっている
為、入力電力の減衰を小さくする事ができる。更に、ゲ
ート電極のフィンガを長くする事ができる為、半導体装
置の高出力化が容易に実現できる。。In this embodiment configured in this way, the distance from the gate electrode phase bonding pads 3A, 3B to the electrode fingers 1 to 6 is more effective than when there is only one conventional gate electrode bonding pad. Since the length is short, input power attenuation can be reduced. Furthermore, since the fingers of the gate electrode can be made longer, higher output power of the semiconductor device can be easily achieved. .
以上説明したように本発明は、２個のゲート電極用ボン
ディングパッドを用い、ゲート電極のフィン力の両端か
ら入力電力を供給するように構成し、ケー１へ電極のフ
ィンガ等による抵抗や寄生インダクタンスによる入力電
力の減衰を小さくする事により高出力化が可能な電界効
果トランジスタが得られる効果かある。As explained above, the present invention uses two bonding pads for gate electrodes and is configured to supply input power from both ends of the fin force of the gate electrode. By reducing the attenuation of the input power caused by this, it is possible to obtain a field effect transistor that can achieve high output.
図面の＠１１′Ｌな説明
第１図は本発明の一実施例の平面図、第２図は従来の電
界効果トランジスタの平面図である。DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view of an embodiment of the present invention, and FIG. 2 is a plan view of a conventional field effect transistor.
ｌ・・・ドレイン電極相ボンディングパ・・ｌド、２・
・・ソース電極相ボンディングバ・ソド、３．３Ａ、３
Ｂ・・・グーｌ−電極用ボンディン′グバッド、４・・
・ドレイン電極のフィンガ、５・・・ソース電極のフィ
ンガ、す・・・ケート電極のフィンガ、７Ａ、７Ｂ・・
・ゲート電極の接続部。l...Drain electrode phase bonding pad...l do, 2...
... Source electrode phase bonding bar, 3.3A, 3
B...Glue bonding pad for electrode, 4...
・Drain electrode finger, 5...source electrode finger, s...gate electrode finger, 7A, 7B...
・Gate electrode connection.
Claims (1)
ス領域とドレイン領域と、該ソース領域とドレイン領域
間に形成されたゲート酸化膜と、前記ソース領域とドレ
イン領域及びゲート酸化膜上に形成されたソース電極と
ドレイン電極及びゲート電極とを有する電界効果トラン
ジスタにおいて、前記ゲート電極は２個のボンディング
パッドを有しかつ該２個のボンディングパッドはゲート
電極のフィンガの長手方向の対向する位置に形成されて
いる事を特徴とする電界効果トランジスタ。A source region and a drain region made of an impurity diffusion layer formed on a semiconductor substrate, a gate oxide film formed between the source region and the drain region, and a gate oxide film formed on the source region, the drain region and the gate oxide film. In a field effect transistor having a source electrode, a drain electrode, and a gate electrode, the gate electrode has two bonding pads, and the two bonding pads are formed at opposing positions in the longitudinal direction of the fingers of the gate electrode. A field effect transistor characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61030009A JPS62188275A (en) | 1986-02-13 | 1986-02-13 | Field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61030009A JPS62188275A (en) | 1986-02-13 | 1986-02-13 | Field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62188275A true JPS62188275A (en) | 1987-08-17 |
Family
ID=12291872
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61030009A Pending JPS62188275A (en) | 1986-02-13 | 1986-02-13 | Field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62188275A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0320082A (en) * | 1989-06-16 | 1991-01-29 | Matsushita Electric Ind Co Ltd | Field-effect transistor and integrated circuit using same |
| US5345194A (en) * | 1991-07-23 | 1994-09-06 | Nec Corporation | FET having two gate bonding pads for use in high frequency oscillator |
| US9048196B2 (en) | 2004-09-13 | 2015-06-02 | International Rectifier Corporation | Power semiconductor package |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6092667A (en) * | 1983-10-27 | 1985-05-24 | Fujitsu Ltd | Mis transistor |
| JPS60103672A (en) * | 1983-11-10 | 1985-06-07 | Nec Corp | Semiconductor device |
-
1986
- 1986-02-13 JP JP61030009A patent/JPS62188275A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6092667A (en) * | 1983-10-27 | 1985-05-24 | Fujitsu Ltd | Mis transistor |
| JPS60103672A (en) * | 1983-11-10 | 1985-06-07 | Nec Corp | Semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0320082A (en) * | 1989-06-16 | 1991-01-29 | Matsushita Electric Ind Co Ltd | Field-effect transistor and integrated circuit using same |
| US5345194A (en) * | 1991-07-23 | 1994-09-06 | Nec Corporation | FET having two gate bonding pads for use in high frequency oscillator |
| US9048196B2 (en) | 2004-09-13 | 2015-06-02 | International Rectifier Corporation | Power semiconductor package |
| US9620471B2 (en) | 2004-09-13 | 2017-04-11 | Infineon Technologies Americas Corp. | Power semiconductor package with conductive clips |
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