JPS6298670A - Field effect type semiconductor device - Google Patents
Field effect type semiconductor deviceInfo
- Publication number
- JPS6298670A JPS6298670A JP60238656A JP23865685A JPS6298670A JP S6298670 A JPS6298670 A JP S6298670A JP 60238656 A JP60238656 A JP 60238656A JP 23865685 A JP23865685 A JP 23865685A JP S6298670 A JPS6298670 A JP S6298670A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- semiconductor device
- field effect
- type semiconductor
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 57
- 230000005669 field effect Effects 0.000 title claims abstract description 38
- 239000000758 substrate Substances 0.000 claims description 5
- 230000000694 effects Effects 0.000 claims description 4
- 230000002159 abnormal effect Effects 0.000 abstract description 6
- 230000010355 oscillation Effects 0.000 abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 3
- 229920005591 polysilicon Polymers 0.000 abstract description 3
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 241000288673 Chiroptera Species 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 210000000078 claw Anatomy 0.000 description 1
- 230000005685 electric field effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、電界効果型半導体装置に関し、特に多数並
列接続動作を改善した電界効果型半導体装置に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a field effect semiconductor device, and particularly to a field effect semiconductor device with improved multiple parallel connection operation.
第３図は従来の電界効果型半導体装置としてのパワーＭ
ＯＳ電界効果トランジスタ（以下、電界効果トランジス
タをＦＥＴと略記する）を示す断面図である。図におい
て、（ｌａ）は第１Ｒ電形高濃度ドレイン領域（１ｂ）
の表面に形成された第１導電形低４度ドレイン領域、（
１ｂ）は半導体基板である第１導電形高濃度ドレイン領
域（１ｂ）、（２）は第１導電形低ｌ農度ドレイン領域
（１ａ）の表面に形成された複数の第２導電形半導体領
域、（３）は各第２導電形半導体領域（２）内に中央部
を開けて形成された第１導電形ソース領域、（４）は各
第２導電形半導体領域（２）間の第１導電形低濃度ドレ
イン領域（１ａ）の表面、第１導電形ドレイン低濃度領
域（ｌａ）と各第１導電形ソース領域（３）間の各第２
導電形半導体領域（２）の表面および各第１導電形ソー
ス領域（３）の表面の一部に形成された絶縁膜、（５）
は！！！！縁膜（４）の表面に形成されたゲート電極、
（６）は各第１導電形ソース領域（３）の表面の一部お
よびソース領域（３）の中央部の第２導電形半導体領域
（２）の表面に絶縁膜（４）を介して形成されたソース
電極、（７）は第２導電形半導体領域（２）の一部でな
るチャネル形成領域、（８）は第１導電形半導体領域（
１））の下面に形成されたドレイン電極、（２１）は各
第２導電形半導体領域（２）の凸部である。Figure 3 shows the power M as a conventional field effect semiconductor device.
1 is a cross-sectional view showing an OS field effect transistor (hereinafter, a field effect transistor is abbreviated as FET). In the figure, (la) is the first R type high concentration drain region (1b)
A first conductivity type low 4 degree drain region formed on the surface of (
1b) is a first conductivity type high concentration drain region (1b) which is a semiconductor substrate, and (2) is a plurality of second conductivity type semiconductor regions formed on the surface of the first conductivity type low concentration drain region (1a). , (3) is a first conductivity type source region formed in each second conductivity type semiconductor region (2) with an opening in the center, and (4) is a first conductivity type source region between each second conductivity type semiconductor region (2). The surface of the conductivity type low concentration drain region (1a), each second conductivity type drain region (la) between the first conductivity type low concentration drain region (la) and each first conductivity type source region (3).
an insulating film (5) formed on the surface of the conductive type semiconductor region (2) and a part of the surface of each first conductive type source region (3);
teeth! ! ! ! a gate electrode formed on the surface of the membrane (4);
(6) is formed on a part of the surface of each first conductivity type source region (3) and on the surface of the second conductivity type semiconductor region (2) in the center of the source region (3) via an insulating film (4). (7) is a channel forming region which is a part of the second conductivity type semiconductor region (2), (8) is the first conductivity type semiconductor region (
The drain electrode (21) is a convex portion of each second conductive type semiconductor region (2).
パワーＭＯ３ＦＥＴは、このような基本ユニットが多数
並列接続された構造をしている。The power MO3FET has a structure in which a large number of such basic units are connected in parallel.
第４図（ａｌおよび（ｂｌは、パワーＭＯ３ＦＥＴの平
面図および断面図であり、特にゲートボンディングパッ
ト部を示す。図において、（５１）はゲート配線電極で
ゲートボンディングパソト部となり、その下には第２導
電形半導体領域（１０）が形成されている。また、（６
１）はソースボンディングパワ）部である。Figure 4 (al and (bl) are a plan view and a cross-sectional view of the power MO3FET, especially showing the gate bonding pad part. In the figure, (51) is the gate wiring electrode and becomes the gate bonding pad part, and below it A second conductivity type semiconductor region (10) is formed in (6).
1) is the source bonding power section.
次に動作について説明する。ドレイン電極（８）とソー
ス電極（６）間にドレイン電圧を印加した状態でゲート
電極（５）とソース電極（６）間にゲート電圧を印加す
ると、チャネル形成領域（７）にチャネルが形成され、
ドレイン電極（８）とソース電極（６）間にドレイン電
流が流れる。このとき、ゲート電極（５）とソース電極
（６）間に印加するゲート電圧を制御することによって
、ドレイン電極（８）とソース電極（６）間を流れるド
レイン電流を制御することができる。ソース電極（６）
による第２導電形半導体領域（２）とソース領域（３）
との短絡は、チャネル形成領域（７）の電位を固定させ
るために不可欠である。Next, the operation will be explained. When a gate voltage is applied between the gate electrode (5) and the source electrode (6) while a drain voltage is applied between the drain electrode (8) and the source electrode (6), a channel is formed in the channel formation region (7). ,
A drain current flows between the drain electrode (8) and the source electrode (6). At this time, the drain current flowing between the drain electrode (8) and the source electrode (6) can be controlled by controlling the gate voltage applied between the gate electrode (5) and the source electrode (6). Source electrode (6)
second conductivity type semiconductor region (2) and source region (3)
A short circuit with the channel forming region (7) is essential for fixing the potential of the channel forming region (7).
ところで、パワーＭＯ３ＦＥＴは、少数キャリアの注入
、蓄積が基本的に問題にならないために高速動作が可能
であるが、その反面バイポーラトランジスタやサイリス
クでは少数キャリアによる伝】！１度変調により高抵抗
領域のオン抵抗がないため、オン抵抗がバイポーラ素子
に比べて大きい。By the way, power MO3FETs are capable of high-speed operation because the injection and accumulation of minority carriers is basically not a problem, but on the other hand, bipolar transistors and SIRISKs are capable of high-speed operation due to minority carriers. Since there is no on-resistance in the high-resistance region due to one-time modulation, the on-resistance is larger than that of a bipolar element.
従来の電界効果型半導体装置は以上のように構成されて
いるので、電界効果型半導体装ことしてのパワーＭＯ３
ＦＥＴの電流容量増大のためには、パワーＭＯＳ Ｆ
ＥＴの活性部の周辺長の増大と、高抵抗領域である第１
導電形低濃度ドレイン領域（ｌａ）の薄層化が必要であ
る。パワーＭＯ３ＦＥＴの活性部の周辺長の増大のため
の節単な方法としてパワーＭＯＳ Ｆ ＥＴを多数並列
接続する方法があるが、多数並列接続した場合には動作
時に異常発振するなどのおそれがあった。Since the conventional field effect semiconductor device is configured as described above, the power MO3 as the field effect semiconductor device is
In order to increase the current capacity of FET, power MOS F
The increase in the peripheral length of the active region of ET and the first
It is necessary to make the conductive type lightly doped drain region (la) thinner. A simple method for increasing the peripheral length of the active part of a power MO3FET is to connect a large number of power MOSFETs in parallel, but when a large number of power MOSFETs are connected in parallel, there is a risk of abnormal oscillation during operation. .
そこで、従来は多数並列接続時の異常発振を防止するた
めに、電界効果型半導体装置のゲート電極に直列に抵抗
を外付けしていたが、この抵抗の外付けには工数を要し
半導体装置が尚価になるとともに、精度の高い制御がで
きないという問題点があった。Conventionally, a resistor was externally attached in series to the gate electrode of a field effect semiconductor device in order to prevent abnormal oscillations when a large number of devices are connected in parallel. There were problems in that it was expensive and that highly accurate control was not possible.
この発明は上記のような問題点を解消するためになされ
たもので、縦方向に主電流の経路を有する電界効果型半
導体装置において、多数並列接続時にゲート電極への抵
抗の外付けを必要としない電界効果型半導体装置を提供
することを目的とする。This invention was made to solve the above-mentioned problems, and it is necessary to externally attach a resistor to the gate electrode when connecting a large number of devices in parallel in a field effect semiconductor device having a main current path in the vertical direction. The object of the present invention is to provide a field-effect semiconductor device that does not
また、この発明の別の発明は、横方向に主電流の経路を
存する電界効果型半導体装置において、多数並列接続時
にゲート電極への抵抗の外付けを必要としない電界効果
型半導体装置を提供することを目的とする。Another invention of the present invention is to provide a field effect semiconductor device in which a main current path exists in the lateral direction, which does not require external resistance to the gate electrode when a large number of parallel connections are made. The purpose is to
〔問題点を解決するための手段〕
この発明に係る電界効果型半導体装置は、縦方向に主電
流の経路を有する電界効果型半導体装置において、ゲー
ト配線電極のボンディングバソト部を分離し、ゲート配
線電極とゲートポンディングパント間の絶縁股上に爪抗
体を形成したものである。[Means for Solving the Problems] A field effect semiconductor device according to the present invention is a field effect semiconductor device having a main current path in the vertical direction, in which the bonding base portion of the gate wiring electrode is separated, and the gate A claw antibody is formed on the insulating crotch between the wiring electrode and the gate bonding punt.
また、この発明の別の発明に係る電界効果型半導体装置
は、横方向に主電流の経路を有する電界効果型半導体装
置において、ゲート配線電極のポンディングパソト部を
分離し、ゲート配線電極とゲートボンディングバット間
の絶縁膜上に抵抗体を形成したものである。Further, in a field effect semiconductor device according to another aspect of the present invention, in a field effect semiconductor device having a main current path in the lateral direction, a bonding portion of a gate wiring electrode is separated from the gate wiring electrode. A resistor is formed on an insulating film between gate bonding bats.
この発明における電界効果型半導体装置は、縦方向に主
電流の経路を有する電界効果型半導体装置において、ゲ
ート電極に直列に抵抗を備えることにより、電界効果に
て動作する領域は抵抗成分によってスイッチング速度が
緩和され、多数並列接続にて動作した場合の異常発振を
防ぐことができる。The field effect semiconductor device according to the present invention has a main current path in the vertical direction, and by providing a resistor in series with the gate electrode, a region that operates by the field effect has a switching speed due to the resistance component. is alleviated, and abnormal oscillations can be prevented when operating in multiple parallel connections.
この発明の別の発明における電界効果型半導体装置は、
横方向に主電流の経路を有する電界効果型半導体装置に
おいて、ゲート電極に直列に抵抗を備えることにより、
電界効果にて動作する領域は抵抗成分によってスイッチ
ング速度が緩和され、多数並列接続にて動作した場合の
異常発振を防ぐことができる。A field effect semiconductor device according to another invention of the present invention includes:
In a field effect semiconductor device having a main current path in the lateral direction, by providing a resistor in series with the gate electrode,
In the region that operates by electric field effect, the switching speed is moderated by the resistance component, and it is possible to prevent abnormal oscillation when operating in a large number of parallel connections.
以下、この発明の一実施例を図について説明する。第１
図（ａｌ、 ｆｂｌにおいて、（１ａ）、（１ｂ）、（
２）〜（８）、（１０）、（２１）、（５１）、（６１
）は第４図（ａｌ、 ｆｂｌに示した従来の電界効果型
半導体装置におけるものと同様のものである。（９）は
ゲート電線電極（５１）とゲートボンディングバラｌ−
（５２）間の絶縁膜（４）上に形成されたゲート直列抵
抗（５０〜１５０Ω） 、（５２）はゲート電線電極（
５１）から分離されたゲートボンディングパットである
。An embodiment of the present invention will be described below with reference to the drawings. 1st
In figures (al, fbl, (1a), (1b), (
2) to (8), (10), (21), (51), (61
) is similar to that in the conventional field effect semiconductor device shown in Fig. 4 (al, fbl).
(52) is the gate series resistance (50 to 150Ω) formed on the insulating film (4), (52) is the gate wire electrode (
This is a gate bonding pad separated from 51).
ゲート直列抵抗（９）としてポリシリコン抵抗を用い、
抵抗値のコントロールはイオン注入技術を用いてコント
ロールすることができる。A polysilicon resistor is used as the gate series resistor (9),
The resistance value can be controlled using ion implantation technology.
このように、電界効果型半導体装τのゲート電極に直列
な抵抗体を半導体装置内に形成することにより、外付は
抵抗と同様に電界効果にて動作する領域がゲート直列抵
抗成分によってスイッチング速度が緩和され、多数並列
接続にて動作したときの異常発振を防ぐことができる。In this way, by forming a resistor in series with the gate electrode of the field-effect semiconductor device τ in the semiconductor device, the external region that operates by the field effect like a resistor increases the switching speed due to the gate series resistance component. is alleviated, and abnormal oscillations can be prevented when operating in multiple parallel connections.
第２図（ａｌ、 （ｂｌはこの発明の他の実施例による
電界効果型半導体装置の平面図および断面図である。FIGS. 2A and 2B are a plan view and a sectional view of a field effect semiconductor device according to another embodiment of the present invention.
ゲート電極（５）にポリシリコンを使用した場合で、ゲ
ート直列抵抗（９）をゲート電極（５）と同時に形成す
ることができる。このときのゲート直列抵抗（９）の抵
抗値は、ゲート直列抵抗（９）のパターン幅を写真製版
技術を用いて制御することによって得られる。When polysilicon is used for the gate electrode (5), the gate series resistor (9) can be formed simultaneously with the gate electrode (5). The resistance value of the gate series resistor (9) at this time is obtained by controlling the pattern width of the gate series resistor (9) using photolithography.
（発明の効果〕
以上のように、この発明によれば縦方向に主電流の経路
を有する電界効果型半導体装置内にゲート直列抵抗を形
成するように構成したので、多数並列接続動作を改善し
た縦方向に主電流の経路を存する電界効果型半導体装置
が安価にでき精度の高いものが得られる効果がある。(Effects of the Invention) As described above, according to the present invention, since a gate series resistance is formed in a field effect semiconductor device having a main current path in the vertical direction, multiple parallel connection operations are improved. This has the effect that a field effect semiconductor device having a main current path in the vertical direction can be produced at low cost and with high precision.
また、本発明の別の発明によれば横方向に主電流の経路
を有する電界効果型半導体装置内にゲート直列抵抗を形
成するように構成したので、多数並列接続動作を改善し
た横方向に主電流の経路を有する電界効果型半導体装置
が安価にでき精度の高いものが得られる効果がある。According to another aspect of the present invention, the gate series resistance is formed in a field effect semiconductor device having a main current path in the lateral direction, so that the main current flow is mainly in the lateral direction, which improves the operation of multiple parallel connections. This has the advantage that a field effect semiconductor device having a current path can be produced at low cost and with high precision.
第１図（ａｔ、 （ｂｌはこの発明の一実施例による電
界効果型半導体装置の平面図および断面図、第２図ｔａ
ｇ、 （ｂｌはこの発明の他の実施例による電界効果型
半導体装置の平面図および断面図、第３図は従来の電界
効果型半導体装置の一例を示す断面図、第４図（ａｌ、
（ｂｌは従来の電界効果型半導体装置の他の例を示す
平面図および断面図である。
（１ａ）は第１導電形低濃度ドレイン領域、（１ｂ）は
第１導電形高沼度ドレイン領域、（２１，（１０）は第
２導電形半可体領域、（３）は第１導電形ソース領域、
（４）は絶縁膜、（５）はゲート電極、（６）はソース
電極、（７）はチャネル形成領域、（８）はドレイン電
掘、（９）はゲート直列抵抗、（５１）はゲート配線電
極、（５２）はゲートボンディングパット。
なお、各図中同一符号は同一または相当部分を示す。Figure 1 (at, (bl) is a plan view and cross-sectional view of a field effect semiconductor device according to an embodiment of the present invention, Figure 2 (ta)
g, (bl is a plan view and a cross-sectional view of a field-effect semiconductor device according to another embodiment of the present invention, FIG. 3 is a cross-sectional view showing an example of a conventional field-effect semiconductor device, and FIG. 4 (al,
(bl is a plan view and a cross-sectional view showing another example of a conventional field effect semiconductor device. (1a) is a first conductivity type low concentration drain region, (1b) is a first conductivity type high concentration drain region , (21, (10) is a second conductivity type semi-solid region, (3) is a first conductivity type source region,
(4) is an insulating film, (5) is a gate electrode, (6) is a source electrode, (7) is a channel formation region, (8) is a drain trench, (9) is a gate series resistance, (51) is a gate Wiring electrode, (52) is gate bonding pad. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (2)
される第２導電形半導体領域と、この第２導電形半導体
領域内のその表面に中央部をあけて形成される第１導電
形半導体領域と、前記基板と前記第１導電形半導体領域
間の前記第２導電形半導体領域の表面に形成される絶縁
膜と、この絶縁膜の表面に形成されるゲート電極とを備
え、縦方向に主電流の経路を有する電界効果型半導体装
置において、２つの部分に分離された前記ゲート電極と
、前記２つの部分間を接合する前記絶縁膜上に形成され
た抵抗体とを備えることを特徴とする電界効果型半導体
装置。(1) A first conductivity type semiconductor substrate, a second conductivity type semiconductor region formed on the surface of this substrate, and a first conductivity type semiconductor region formed on the surface of the second conductivity type semiconductor region with a central portion open therein. a vertical conductivity type semiconductor region, an insulating film formed on the surface of the second conductivity type semiconductor region between the substrate and the first conductivity type semiconductor region, and a gate electrode formed on the surface of the insulating film; A field effect semiconductor device having a main current path in a direction, comprising: the gate electrode separated into two parts; and a resistor formed on the insulating film connecting the two parts. Features of field effect semiconductor device.
分離された第２導電形半導体領域と、これら第２導電形
半導体領域間に形成される絶縁膜と、この絶縁膜の表面
に形成されるゲート電極とを備え、横方向に主電流の経
路を有する電極効果型半導体装置において、２つの部分
に分離された前記ゲート電極と、前記２つの部分間を接
合する前記絶縁膜上に形成された抵抗体とを備えること
を特徴とする電界効果型半導体装置。(2) two separated second conductivity type semiconductor regions formed on the surface of the first conductivity type semiconductor substrate; an insulating film formed between these second conductivity type semiconductor regions; In an electrode effect type semiconductor device having a main current path in the lateral direction, the gate electrode is formed on the gate electrode separated into two parts, and the insulating film joining the two parts. A field effect semiconductor device comprising a resistor formed therein.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60238656A JPH0758781B2 (en) | 1985-10-24 | 1985-10-24 | Field effect semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60238656A JPH0758781B2 (en) | 1985-10-24 | 1985-10-24 | Field effect semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6298670A true JPS6298670A (en) | 1987-05-08 |
| JPH0758781B2 JPH0758781B2 (en) | 1995-06-21 |
Family
ID=17033369
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60238656A Expired - Lifetime JPH0758781B2 (en) | 1985-10-24 | 1985-10-24 | Field effect semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0758781B2 (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62115875A (en) * | 1985-11-15 | 1987-05-27 | Nec Corp | Vertical field effect transistor |
| JPH01305576A (en) * | 1988-06-03 | 1989-12-08 | Fujitsu Ltd | Mis type field effect transistor |
| JPH0242764A (en) * | 1988-08-01 | 1990-02-13 | Toshiba Corp | Vertical type mosfet |
| EP0736907A1 (en) * | 1995-04-05 | 1996-10-09 | Siemens Aktiengesellschaft | Semiconductor field effect device with an integrated ohmic resistance |
| WO2011014290A1 (en) * | 2009-07-28 | 2011-02-03 | Cree, Inc. | Semiconductor devices including electrodes with integrated resistances and related methods |
| JP2014216352A (en) * | 2013-04-22 | 2014-11-17 | 新電元工業株式会社 | Semiconductor device and semiconductor device manufacturing method |
| US9048116B2 (en) | 2011-12-07 | 2015-06-02 | Nxp B.V. | Semiconductor device having isolation trenches |
| EP3076431A4 (en) * | 2013-11-28 | 2017-08-09 | Rohm Co., Ltd. | Semiconductor device |
| WO2022187018A1 (en) * | 2021-03-01 | 2022-09-09 | Wolfspeed, Inc. | Semiconductor devices having gate resistors with low variation in resistance values |
| WO2024101130A1 (en) * | 2022-11-08 | 2024-05-16 | ローム株式会社 | Semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4932474A (en) * | 1972-07-24 | 1974-03-25 | ||
| JPS5830151A (en) * | 1981-08-18 | 1983-02-22 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPS60171771A (en) * | 1984-02-17 | 1985-09-05 | Hitachi Ltd | Insulated gate semiconductor device |
-
1985
- 1985-10-24 JP JP60238656A patent/JPH0758781B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4932474A (en) * | 1972-07-24 | 1974-03-25 | ||
| JPS5830151A (en) * | 1981-08-18 | 1983-02-22 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPS60171771A (en) * | 1984-02-17 | 1985-09-05 | Hitachi Ltd | Insulated gate semiconductor device |
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62115875A (en) * | 1985-11-15 | 1987-05-27 | Nec Corp | Vertical field effect transistor |
| JPH01305576A (en) * | 1988-06-03 | 1989-12-08 | Fujitsu Ltd | Mis type field effect transistor |
| JPH0242764A (en) * | 1988-08-01 | 1990-02-13 | Toshiba Corp | Vertical type mosfet |
| EP0736907A1 (en) * | 1995-04-05 | 1996-10-09 | Siemens Aktiengesellschaft | Semiconductor field effect device with an integrated ohmic resistance |
| WO2011014290A1 (en) * | 2009-07-28 | 2011-02-03 | Cree, Inc. | Semiconductor devices including electrodes with integrated resistances and related methods |
| US8314462B2 (en) | 2009-07-28 | 2012-11-20 | Cree, Inc. | Semiconductor devices including electrodes with integrated resistances |
| JP2013500604A (en) * | 2009-07-28 | 2013-01-07 | クリー インコーポレイテッド | Semiconductor device including electrodes with integrated resistance and related techniques |
| US9048116B2 (en) | 2011-12-07 | 2015-06-02 | Nxp B.V. | Semiconductor device having isolation trenches |
| JP2014216352A (en) * | 2013-04-22 | 2014-11-17 | 新電元工業株式会社 | Semiconductor device and semiconductor device manufacturing method |
| US9917102B2 (en) | 2013-11-28 | 2018-03-13 | Rohm Co., Ltd. | Semiconductor device |
| EP3076431A4 (en) * | 2013-11-28 | 2017-08-09 | Rohm Co., Ltd. | Semiconductor device |
| US10438971B2 (en) | 2013-11-28 | 2019-10-08 | Rohm Co., Ltd. | Semiconductor device |
| EP3644363A1 (en) * | 2013-11-28 | 2020-04-29 | Rohm Co., Ltd. | Semiconductor device |
| US10886300B2 (en) | 2013-11-28 | 2021-01-05 | Rohm Co., Ltd. | Semiconductor device |
| US11367738B2 (en) | 2013-11-28 | 2022-06-21 | Rohm Co., Ltd. | Semiconductor device |
| EP4141953A1 (en) * | 2013-11-28 | 2023-03-01 | Rohm Co., Ltd. | Semiconductor device |
| US11908868B2 (en) | 2013-11-28 | 2024-02-20 | Rohm Co., Ltd. | Semiconductor device |
| WO2022187018A1 (en) * | 2021-03-01 | 2022-09-09 | Wolfspeed, Inc. | Semiconductor devices having gate resistors with low variation in resistance values |
| US11664436B2 (en) | 2021-03-01 | 2023-05-30 | Wolfspeed, Inc. | Semiconductor devices having gate resistors with low variation in resistance values |
| WO2024101130A1 (en) * | 2022-11-08 | 2024-05-16 | ローム株式会社 | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0758781B2 (en) | 1995-06-21 |
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