JPS6375679A - Semiconductive integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the leak current flowing to an output buffer circuit, by performing the incremental control of the ON-resistance of a transfer gate circuit. CONSTITUTION:The respective output buffer circuits Buff1, Buffi connected to an internal bus IB are set to the try state system connected to the bus IB through transfer gate circuits TG1, TGi constituted of complementary type MOS circuits Q3, Q4 and, at the setting time of a test mode, the ON-resistances of the circuits TG1, TGi are controlled so as to be increased over those at the time of an usual operation mode. By this method, the reduction of the leak current flowing to the circuits Buff1, Buffi having the internal bus IB in common can be achieved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a technology for reducing leakage current when detecting a failure in a semiconductor integrated circuit, and relates to a technology that is effective when applied to, for example, a gate array circuit with a self-diagnosis function. It is something.

[Prior art]

2. Description of the Related Art As a technique for facilitating tests such as failure detection in semiconductor integrated circuits, there is a technique called LSSD (Level Sensitive Scan Design) or scan path method. In order to efficiently test the increasing number of logic gates from a small number of external terminals, such test facilitation technology provides a data input/output mode for testing separately from the normal operation mode, and stores test pattern data in internal circuits. This is a method that allows tests to be easily performed by inputting and outputting data.
As described in 2S5, a sequential circuit such as a flip-flop circuit in a semiconductor integrated circuit is configured to operate as a register-like circuit in a test mode, and such a register can be externally tested in a test mode. By inputting and outputting pattern data.

All internal circuits can be treated as combinational circuits,
Thereby, it is intended to realize a self-diagnosis function of a semiconductor integrated circuit based on a test pattern.

By the way, in a gate array circuit equipped with a self-diagnosis function using such testability technology, when multiple tri-state output buffer circuits included in the circuit share an internal bus, in normal operation mode, the internal Although the output buffer circuits that share the bus are not output-enabled at the same time, the test pattern data supplied in test mode is created as the most effective pattern of input data to achieve high fault coverage. Therefore, in some cases, a plurality of output buffer circuits each having an internal bus ib may be put into an output enabled state at the same time.

[Problem that the invention seeks to solve]

However, if multiple tri-state output buffer circuits that share an internal bus are enabled at the same time, leakage current may occur through the internal bus depending on the output level of the output buffer circuits in the output enabled state. There is. For example, if each output sofa circuit is composed of complementary MOS clocked inverter circuits, if the output levels of the multiple clocked inverter circuits that are set to the output enabled state are different, the clocked inverter circuit that outputs a high level will The current supplied to the bus flows to the ground terminal via the clocked inverter circuit that outputs a low level. The current value that flows at this time varies depending on the number of output buffer circuits that share the internal bus and are in the output enabled state, and the difference in the output level of the output buffer circuits, but depending on the test pattern, the allowable value may vary. There is a risk that a large current in excess of

An object of the present invention is to provide a semiconductor integrated circuit that can reduce leakage current that may flow through an internal bus to a tri-state output buffer circuit that shares the internal bus in a test mode. It is in.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, each of the seven output buffer circuits commonly connected to the internal bus is a tri-state type connected to the internal bus via a transfer gate circuit such as a complementary MO3 circuit, and when setting the test mode, , the on-resistance of these transfer gate circuits is controlled to be greater than that in the normal operation mode.

[For production]

According to the above-described means, the on-resistance of the transfer gate circuit in the test mode is increased compared to that in normal operation, so that in the test mode, the output sofa circuit shares the internal bus via the internal bus. This achieves the reduction of leakage current that may flow in the device.

〔Example〕

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

The circuit shown in FIG. 1 is applied to a gate array circuit having a self-diagnosis function using a scan path or LSSD method, although it is not particularly limited, and is a well-known complementary MO3 (hereinafter also simply referred to as 0MOS) integrated circuit. It is formed on one semiconductor substrate using manufacturing technology.

In the figure, B uff to B uff are tri-state output sofa circuits that share the internal bus B. Each output buffer circuit Buff is a P-channel type MO5.
A P-channel type MOSFET Q3 and an N-channel type MOSFET Q4 are connected in parallel to the output terminal of a CMOS inverter circuit IV (or IVi) formed by connecting an FET Q1 and an N-channel type MOSFET Q2 in series to a power supply terminal Vdd and a ground terminal G n d. The drain and source electrodes of one of the CMOS transfer gate circuits TO1 (or TGi) are coupled together, and the drain and source electrodes of the other transfer gate circuit TO1 (or TGi) are coupled together. The poles are configured to be connected to a bipedal internal bus IB.

Data D1 to Dj are supplied to each of the CMOS inverter circuits IV to IVi from inside the gate array circuit. E□ to Ei are the above commercials
This is a control signal for selectively controlling each of the OSt-transfer gate circuits TG1 to TGi to output enable or output disable, and the control signal is directly supplied to the gate electrode of MOSFETQ4,
The gate electrode of TQ3 receives its control signal and test signal T.
The output signal of the NAND gate circuit NAND, which is operated by two people, is supplied. The test signal T is set to a low level in response to the test mode being set in the gate array circuit. As a result, in the test mode, the output signal of the NAND gate circuit NAND is always at a high level regardless of the levels of the control signals El to Ei, so that the CMOS! - MO3FETs forming transfer gate circuits TG1 to 'I' G i
Q3 is always in the OFF state, thereby increasing the on-resistance of the CMOS transfer gate circuits TG1 to TG i in the test mode, and the current transfer capability thereof is approximately half of that in the normal operation mode. .

Therefore, in the test mode, when a plurality of output buffer circuits B uff to Buffj, for example output buffer circuits B uff and B uffj, are put into an output enable state by high-level control signals E1 and Ei, the output buffer circuits The circuit B uff outputs high level data, and the output buffer circuit B
Even if uffi outputs low level data, the CMOS inverter circuit IV,
CMOS inverter circuit IV from MOSFETQ1
i (7) MOSFET Q 2 The current flowing through the LC is approximately halved compared to the case where both MOSFETs Q3 and Q4 are in the on state.

In normal operation mode, the output buffer circuits Buff and Buffi that share the internal bus IB are not enabled at the same time, but testing of gate array circuits equipped with self-diagnosis functions using testability technology In the mode, the test pattern data supplied to it is created and set as the most effective input data pattern to achieve a high failure coverage rate, so as described above, the test pattern data supplied to the output buffer circuit B uff
There are cases where a plurality of uffi are output enabled at the same time, and in that case, the leakage current flowing through the internal bus IB is transferred to the transfer gate circuit TG to TG.
is halved by the increase in the on-resistance of i, thereby
Regardless of the test pattern, in other words, even if all the output buffer circuits are in the output enable state and take different output level states, the internal bus I
The possibility that a large current that exceeds the allowable value will flow as a leakage current, which could cause a circuit failure due to burning of B, is significantly reduced. In particular, transfer gate circuits TG to T
If the on-resistance of Gi is increased, it will take time to determine the output data, but in test mode for circuits such as gate array circuits, it is sufficient to be able to detect DC errors for various functional blocks. Therefore, high speed for test l- is not required and does not pose any problem.

According to the two-legged embodiment, the following effects can be obtained.

(1) By keeping the MO3FETQ3 of the CMOS transfer gate circuit TG to TGi in the off state at all times in response to the test mode setting, the on-resistance of the CMO3I-transfer gate circuit TG to TGi is increased. , the current transfer capability is reduced by almost half, so multiple output buffer circuits Buff to Buffi are put into an output enable state based on the test pattern, and they output data at different levels. Also, the leakage current flowing through the internal bus IB is MO3F.
This is half of the case when both ETQ3 and Q4 are turned on, and this makes it possible to significantly reduce the risk of burning out the internal bus IB due to a large current that exceeds the allowable value flowing as a leakage current. .

(2) The above effects can contribute to improving the reliability of the failure detection function in a gate array circuit with a self-diagnosis function.

Although the invention made by the present inventor has been specifically explained above based on examples, the present invention is not limited to the above-mentioned examples, and various changes can be made without departing from the gist thereof.

for example. In the above embodiment, the output buffer circuit is configured by an inverter circuit and a transfer gate circuit made up of complementary MOS circuits, and in the test mode, one MOSFET constituting the transfer gate 1 circuit is always turned off. Although the on-resistance of such a transfer gate circuit is increased, it is not limited to such a configuration, and the inverter circuit and transfer gate circuit can be of other circuit formats, for example, an N-channel When using a transfer gate circuit and a clocked inverter circuit constituted by type MOSFTs, in the des1-mode, a voltage at a lower level than in the normal operation mode is applied to the gate electrode of the des1-mode. It is only necessary to control the voltage so that the voltage is applied.

In the following explanation, the present invention was mainly applied to the field of application which is the background of the present invention, which is the Go1-F14 circuit with a self-diagnosis function using the LSSD or scan path method, but the present invention is not limited to this. It can be applied to various semiconductor integrated circuits whose failures can be detected by other methods such as a stored response method or a compact test method. The present invention can be applied to at least tri-state output buffer circuits that share an internal bus.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, each output buffer circuit commonly connected to the internal bus is of a tri-state type connected to the internal bus via a transfer gate circuit constituted by a complementary MOS circuit, and when setting the test mode, Since the on-resistance of these transfer gate circuits is controlled to be higher than in normal operation mode, leakage current that may flow through the internal bus to the output buffer circuit that shares the internal bus in test mode is reduced. be able to.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the present invention. Buffl to Buffj...output sofa circuit,
Ql to Q4 MOSFET, I Vl to Ivi...
・CMOS inverter circuit, TG x to TGi-C
MOS transfer game]・Circuit, E□ to Ei...
Control signal, T...test signal, NAND...Nandogoo 1-circuit.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit capable of executing a test mode for failure detection by obtaining data corresponding to an expected value from an output terminal based on test pattern data, the output terminal is connected to an internal bus. Each of the commonly connected output buffer circuits is a tri-state type connected to the above internal bus via a transfer gate circuit, and when setting the test mode, the on-resistance of these transfer gate circuits is controlled to be higher than in the normal operation mode. A semiconductor integrated circuit comprising: 2. The semiconductor integrated device according to claim 1, wherein the transfer gate circuit is composed of a complementary MOS circuit, and one of the elements is controlled to be in an off state at all times during a test mode. circuit. 3. The semiconductor integrated circuit according to claim 1 or 2, wherein the output buffer circuit is included in a gate array circuit.