JPS6373648A - Manufacture of multilayer interconnection - Google Patents
Manufacture of multilayer interconnectionInfo
- Publication number
- JPS6373648A JPS6373648A JP22000086A JP22000086A JPS6373648A JP S6373648 A JPS6373648 A JP S6373648A JP 22000086 A JP22000086 A JP 22000086A JP 22000086 A JP22000086 A JP 22000086A JP S6373648 A JPS6373648 A JP S6373648A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- insulating film
- moisture
- mask
- mask layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000010410 layer Substances 0.000 claims abstract description 107
- 229920001721 polyimide Polymers 0.000 claims abstract description 41
- 239000004642 Polyimide Substances 0.000 claims abstract description 40
- 239000011229 interlayer Substances 0.000 claims abstract description 29
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- 238000009413 insulation Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 13
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 8
- 229910001882 dioxygen Inorganic materials 0.000 description 8
- 229910052750 molybdenum Inorganic materials 0.000 description 8
- 239000011733 molybdenum Substances 0.000 description 8
- 238000001020 plasma etching Methods 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011346 highly viscous material Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000001012 protector Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は多層配線の製造方法、特にポリイミド層間絶縁
膜を用いた多層配線の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a method for manufacturing multilayer wiring, and particularly to a method for manufacturing multilayer wiring using a polyimide interlayer insulating film.
（ロ）従来の技術
ポリイミドは有機高分子で熱硬化性を有する粘性の高い
物質である。熱硬化後は３００〜５００°Ｃの耐熱性と
優れた耐湿性、絶縁性を有し、感光性樹脂と同様にスピ
ンオンによる塗布が可能であるから高温工程終了後の半
導体装置のパシベーションまたは居間絶縁膜として広く
用いられるようになったことは周知である。(b) Prior Art Polyimide is an organic polymer and is a thermosetting, highly viscous substance. After thermosetting, it has heat resistance of 300 to 500°C, excellent moisture resistance, and insulation properties, and can be applied by spin-on like photosensitive resin, so it can be used for passivation of semiconductor devices or insulation for living rooms after high-temperature processing. It is well known that it has come to be widely used as a membrane.
第２図Ａ乃至第２図Ｅを参照して従来の多層配線の製造
方法を説明する。A conventional method for manufacturing multilayer wiring will be described with reference to FIGS. 2A to 2E.
まず第２図Ａに示すように、半導体基板（２１）上に酸
化膜（２２）を介してアルミニウムのスパッタにより形
成きれた第１の金属配線層（２３）を形成される、半導
体基板（２１）表面には所望の拡散Ｊｆｆｌ（２４）が
形成され、フンタクト孔を介して第１の金属配線７１（
２３）とオーミック接触されている。First, as shown in FIG. 2A, a first metal wiring layer (23) completely formed by sputtering aluminum is formed on the semiconductor substrate (21) via an oxide film (22). ) A desired diffusion Jffl (24) is formed on the surface, and the first metal wiring 71 (24) is formed through the contact hole.
23) is in ohmic contact.
次に第２図Ｂに示すように、基板（２１）全面にポリイ
ミド（２５）を塗布し、硬化後全面にポリイミド（２５
）のエツチングマスクとなるモリブデン（２６）を被着
形成する。そしてモリブデン（２６）全面をホトレジス
ト（２７）を塗布して被覆し、選択的にコンタクト孔を
設ける領域上に開口部（２８）を形成する。Next, as shown in FIG. 2B, polyimide (25) is applied to the entire surface of the substrate (21), and after curing, polyimide (25) is applied to the entire surface of the substrate (21).
) is deposited and formed with molybdenum (26) to serve as an etching mask. Then, the entire surface of the molybdenum (26) is coated with photoresist (27), and openings (28) are selectively formed in areas where contact holes are to be provided.
次に第２図Ｃに示すように、パターン出しされたホトレ
ジスト（２７）をマスクとしてモリブデン（２６）を選
択的にエツチングする。このエツチング方法はフレオン
０ 、 Ｉ Ｔｏｒｒ、酸素０ 、０１Ｔｏｒｒのガス
圧で発生されるガスプラズマで行い、モリブデン（２６
）のみをエツチングする。続いて酸素ガスプラズマでホ
トレジスト（２７）を除去する。Next, as shown in FIG. 2C, molybdenum (26) is selectively etched using the patterned photoresist (27) as a mask. This etching method is carried out using gas plasma generated at gas pressures of 0 Freon, I Torr, oxygen 0 and 0.1 Torr, and molybdenum (26
) only. Subsequently, the photoresist (27) is removed using oxygen gas plasma.
次に第２図りに示すように、モリブデン（２６）をマス
クとしてポリイミド（２５）酸素ガスプラズマでエツチ
ングして、第１の配線層（２３）まで達するフンタクト
孔（２９）を形成する。その後フレオンを主成分とする
ガスプラズマでモリブデン（２６）を除去する。Next, as shown in the second diagram, polyimide (25) is etched with oxygen gas plasma using molybdenum (26) as a mask to form a hole (29) reaching the first wiring layer (23). Thereafter, molybdenum (26) is removed using gas plasma containing Freon as a main component.
最後に第２図Ｅに示すように、ポリイミド（２５）上に
アルミニウムより成る第２の金属配線層（３０）を形成
している。この第２の金属配線層（３０）はポリイミド
（２５）全面にアルミニウムもスパッタで被着した後、
所望のパターンにホトエツチングして形成される０本工
程で用いたホトレジスト層は酸素ガスプラズマエツチン
グにより除去きれる。Finally, as shown in FIG. 2E, a second metal wiring layer (30) made of aluminum is formed on the polyimide (25). This second metal wiring layer (30) is formed by sputtering aluminum over the entire surface of the polyimide (25).
The photoresist layer used in the zero step, which is formed by photoetching into a desired pattern, can be completely removed by oxygen gas plasma etching.
斯上した従来の技術は、例えば特開昭５６−１２９３４
３号公報（ＨＯＩＬ ２１／９０）等に記載されている
。The above-mentioned conventional technology is disclosed in, for example, Japanese Patent Application Laid-Open No. 56-12934.
It is described in Publication No. 3 (HOIL 21/90).
（ハ）発明が解決しようとする問題点
衛士した従来の多層配線の製造方法では、ホトレジスト
とポリイミドとは酸素ガスプラズマで両者エツチングさ
れるため、ポリイミド（２５）上にモリブデン（２６）
を被着して微細加工している。このためモリブデン（２
６）のエツチング工程と除去工程を余分に必要とし、製
造工程が複雑化する問題点があった。(c) Problems to be Solved by the Invention In the conventional manufacturing method of multilayer wiring, both photoresist and polyimide are etched with oxygen gas plasma, so molybdenum (26) is etched on polyimide (25).
is coated with fine processing. Therefore, molybdenum (2
There is a problem in that the etching process and removal process (6) are extra necessary, which complicates the manufacturing process.
また第２の配線層（３０）のホトエツチング時に用いた
ホトレジストをプラズマエッチで除去する際に露出され
たポリイミド（２５）もエツチングきれて不要の段差が
第２の配線層（３０）とポリイミド（２５）表面間に生
じる問題点も有していた。In addition, the polyimide (25) that was exposed when the photoresist used for photoetching the second wiring layer (30) was removed by plasma etching was also removed, leaving unnecessary steps between the second wiring layer (30) and the polyimide (25). ) Also had problems that occurred between the surfaces.
（ニ）問題点を解決するための手段
本発明は斯上した問題点に鑑みてなされ、ポリイミド層
間絶縁膜上に耐湿性絶縁マスク層を被着し、この耐湿性
絶縁マスク層を用いてポリイミド層間絶縁膜のエツチン
グを行い、更に耐湿性絶縁マスク層を最後まで残存させ
ることにより、従来の問題点を大巾に改善した多層配線
の製造方法を実現するものである。(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned problems, and involves depositing a moisture-resistant insulating mask layer on a polyimide interlayer insulating film, and using this moisture-resistant insulating mask layer to form a polyimide film. By etching the interlayer insulating film and leaving the moisture-resistant insulating mask layer to the end, a method of manufacturing multilayer interconnection is realized which greatly improves the problems of the conventional method.
（ネ）作用
本発明に依れば、ポリイミド層間絶縁膜のエツチングに
用いる耐湿性絶縁マスク層を最後まで残存させるので、
耐湿性絶縁マスク層の除去工程を省略でき工程の簡略化
を実現できる。(f) Function According to the present invention, the moisture-resistant insulating mask layer used for etching the polyimide interlayer insulating film remains until the end.
The step of removing the moisture-resistant insulating mask layer can be omitted, and the process can be simplified.
また第２の配線層のホトエツチングで用いたホトレジス
ト層を除去する際にポリイミド層間絶縁膜を保護し、不
要のポリイミド層間絶縁膜のエツチングを肪止できる。Further, when removing the photoresist layer used in photo-etching the second wiring layer, the polyimide interlayer insulating film is protected, and unnecessary etching of the polyimide interlayer insulating film can be prevented.
（へ）実施例
本発明による多層配線の製造方法を第１図Ａ乃至第１図
Ｈを参照して詳述する。(F) Embodiment A method of manufacturing a multilayer wiring according to the present invention will be described in detail with reference to FIGS. 1A to 1H.
本発明の第１の工程は第１図Ａに示すように、半導体基
板（１）の絶縁膜（２）上に第１の配線層（３）を形成
することにある。The first step of the present invention, as shown in FIG. 1A, is to form a first wiring layer (3) on an insulating film (2) of a semiconductor substrate (1).
本工程では半導体基板（１）表面に所望の拡散領域（４
）を形成した後、基板（１）表面をシリコン酸化膜より
成る絶縁膜（２）で被覆し、この絶縁膜（２）上にアル
ミニウムのスパッタにより形成された第１の金属配置ａ
層（３）を形成している。なおこの第１の金属配線層（
３）は絶縁膜（２）に設けたコンタクト孔を介して所望
の拡散領域（４）とオーミンク接触している。In this step, desired diffusion regions (4) are formed on the surface of the semiconductor substrate (1).
), the surface of the substrate (1) is covered with an insulating film (2) made of a silicon oxide film, and a first metal arrangement a is formed on this insulating film (2) by sputtering aluminum.
Forming layer (3). Note that this first metal wiring layer (
3) is in ohmink contact with the desired diffusion region (4) via a contact hole provided in the insulating film (2).
本発明の第２の工程は第１図Ｂに示すように、°第１の
配線層（３）を被覆するポリイミド層間絶縁膜（５）を
付着し、その上を耐湿性絶縁マスク層（６）で被覆する
ことにある。In the second step of the present invention, as shown in FIG. ).
本工程では基板（１）全面に液状のポリイミドを塗布し
、硬化して表面の平坦なポリイミド層間絶縁膜（５）を
形成する。ポリイミド居間絶縁膜（５）上には全面にシ
リコン窒化膜（ＳｉＮ）を減圧ＣＶＤ法で付若して耐湿
性絶縁マスク層（６）を形成している。この耐湿性絶縁
マスク層（６）はポリイミド層間絶縁膜（５）のエツチ
ング時にマスクとして働き、その後最後までポリイミド
層間絶縁膜（５）上に残存し、外気からの水分の侵入を
防止している。In this step, liquid polyimide is applied to the entire surface of the substrate (1) and cured to form a polyimide interlayer insulating film (5) with a flat surface. A moisture-resistant insulating mask layer (6) is formed on the entire surface of the polyimide living room insulating film (5) by depositing a silicon nitride film (SiN) by low pressure CVD. This moisture-resistant insulating mask layer (6) acts as a mask during etching of the polyimide interlayer insulating film (5), and then remains on the polyimide interlayer insulating film (5) until the end to prevent moisture from entering from the outside air. .
本発明の第３の工程は第１図Ｃに示すように、耐湿性絶
縁マスク層（６）をホトレジスト層（７）で被覆し、所
望のコンタクト孔（８）を形成する部分を露出すること
にある。The third step of the present invention, as shown in FIG. 1C, is to cover the moisture-resistant insulating mask layer (6) with a photoresist layer (7) and expose the portion where the desired contact hole (8) will be formed. It is in.
本工程では耐湿性絶縁マスク層（６）上にホトレジスト
層（７）を塗布し、第１の配線ｆｆ（３）上のコンタク
ト孔（８）を形成する部分を露出する様に露光現像する
。In this step, a photoresist layer (7) is applied on the moisture-resistant insulating mask layer (6), and exposed and developed to expose the portion on the first wiring ff (3) where the contact hole (8) is to be formed.
本発明の第４の工程は第１図りに示すように、耐湿性絶
縁マスク層（６）をホトレジスト層（７）をマスクとし
て選択的にエツチングした後、ホトレジスト層（７）を
除去することにある。The fourth step of the present invention, as shown in the first diagram, involves selectively etching the moisture-resistant insulating mask layer (6) using the photoresist layer (7) as a mask, and then removing the photoresist layer (7). be.
本工程ではホトレジスト層（７）をマスクとして耐湿性
絶縁マスク層（６）を反応性イオンエツチング（ＲＩＥ
）して、所望のフンタクト孔（８）を形成する領域上の
耐湿性絶縁マスク層（７）を除去する。従って耐湿性絶
縁マスク層（６）にはホトレジスト層（７）と同一のパ
ターンが形成される。続いて酸素ガスプラズマでホトレ
ジスト層（７）をエツチング除去する。In this step, the moisture-resistant insulating mask layer (6) is subjected to reactive ion etching (RIE) using the photoresist layer (7) as a mask.
) to remove the moisture-resistant insulating mask layer (7) over the area where the desired hole (8) is to be formed. Therefore, the same pattern as the photoresist layer (7) is formed in the moisture-resistant insulating mask layer (6). Subsequently, the photoresist layer (7) is etched away using oxygen gas plasma.
本発明の第５の工程は第１図Ｅに示すように、耐湿性絶
縁マスク層（６）をマスクとしてポリイミド層間絶縁膜
（５）をエツチングし所望の第１の配線層〈３）上にコ
ンタクト孔（８）を形成することにある。In the fifth step of the present invention, as shown in FIG. 1E, the polyimide interlayer insulating film (5) is etched using the moisture-resistant insulating mask layer (6) as a mask, and the polyimide interlayer insulating film (5) is etched onto the desired first wiring layer (3). The purpose is to form a contact hole (8).
本工程では耐湿性絶縁マスク層（６）をマスクとして用
い、ポリイミド層間絶縁膜（５）を酸素ガスプラズマエ
ツチングにより第１の配線層り３）まで達するフンタク
ト孔（８）を形成する。なお酸素ガスプラズマエツチン
グでは耐湿性絶縁マスク層（６）および第１の配線層（
３）はエツチングされないので、ポリイミド層間絶縁膜
（５）には耐湿性絶縁マスク層（６）と同形状のフンタ
クト孔（８）を微細加工できる。In this step, using the moisture-resistant insulating mask layer (6) as a mask, a hole (8) reaching the first wiring layer 3) is formed in the polyimide interlayer insulating film (5) by oxygen gas plasma etching. In addition, in oxygen gas plasma etching, the moisture-resistant insulating mask layer (6) and the first wiring layer (
Since layer 3) is not etched, it is possible to microfabricate a hole (8) having the same shape as the moisture-resistant insulating mask layer (6) in the polyimide interlayer insulating film (5).
本発明の第６の工程は第１図Ｆに示すように、耐湿性絶
縁マスク層（６）上に第２の配線層（９）となる金属層
（１０）を被若し、第１図Ｇに示すように、金属層（１
０）をエツチングして所望のパターンの第２の配線層（
９）を形成することにある。The sixth step of the present invention is to cover the moisture-resistant insulating mask layer (6) with a metal layer (10) that will become the second wiring layer (9), as shown in FIG. As shown in G, the metal layer (1
0) to form a second wiring layer (
9).
本工程は本発明の特徴とする点であり、耐湿性絶縁マス
ク層（６）を残存許せたまま耐湿性絶縁マスク層（６）
上にアルミニウムをスパッタして被着した金属層（１０
）で被覆し、金属Ｂ（１０）上を所望の形状のホトレジ
スト層（１１）で被覆する。続イテホトレジストＪｌ（
１１）をマスクとして反応性イオンエツチングを行い、
金属層（１０）をエツチング除去する。この結果耐湿性
絶縁マスク層（６）はポリイミド層間絶縁膜〈５）上に
残り、耐湿性絶縁マスク層＜６）上に所望の第２の配線
層（９）を形成できる。This process is a characteristic feature of the present invention, and the moisture-resistant insulating mask layer (6) is removed while the moisture-resistant insulating mask layer (6) is allowed to remain.
A metal layer (10
) and then coat the metal B (10) with a photoresist layer (11) in the desired shape. Continued Itehotresist Jl (
11) Perform reactive ion etching using as a mask,
The metal layer (10) is etched away. As a result, the moisture-resistant insulating mask layer (6) remains on the polyimide interlayer insulating film (5), and a desired second wiring layer (9) can be formed on the moisture-resistant insulating mask layer (6).
本発明の第７の工程は第１図Ｈに示すように、耐湿性絶
縁マスク層（６）でポリイミド層間絶縁膜（５）を保護
しながらホトレジストＪｉ（１１）を除去することにあ
る。The seventh step of the present invention, as shown in FIG. 1H, consists in removing the photoresist Ji (11) while protecting the polyimide interlayer insulating film (5) with a moisture-resistant insulating mask layer (6).
本工程も本発明の特徴とする点であり、ホトレジスト層
（１１）を酸素ガスプラズマエツチングにより除去する
際に、このエツチングによりポリイミド層間絶縁膜（５
〉もエツチングきれるので耐湿性絶縁マスク層（６）を
残存させてポリイミド層間絶縁膜（５）の不要のエツチ
ングを防止している。この結果耐湿性絶縁マスク層（６
）上に第２の配線層（９）のみが残存し、ポリイミド層
間絶縁膜（５）は全くエツチングされない。この耐湿性
絶縁マスク層（６）はその後製品化されても残存され、
耐湿性の劣るポリイミド層間絶縁膜（５）に代って全面
を被覆するので、製品の耐湿性を大巾に向上できる。This step is also a feature of the present invention, and when the photoresist layer (11) is removed by oxygen gas plasma etching, the polyimide interlayer insulating film (5) is removed by this etching.
) can also be etched completely, so the moisture-resistant insulating mask layer (6) remains to prevent unnecessary etching of the polyimide interlayer insulating film (5). As a result, a moisture-resistant insulating mask layer (6
), only the second wiring layer (9) remains, and the polyimide interlayer insulating film (5) is not etched at all. This moisture-resistant insulating mask layer (6) remains even after it is manufactured into a product,
Since the entire surface is covered instead of the polyimide interlayer insulating film (5) which has poor moisture resistance, the moisture resistance of the product can be greatly improved.
（ト）発明の効果
本発明に依れば、ポリイミド層間絶縁膜（５）のエツチ
ングのマスクとして用いる耐湿性絶縁マスク層（６）は
最後まで残存させるので、従来では別個にマスク層の除
去工程を必要としていたのに対し本発明では耐湿性絶縁
マスク層（６）の除去を不要とし、工程の簡略化を図る
ことができる。(g) Effects of the Invention According to the present invention, the moisture-resistant insulating mask layer (6) used as a mask for etching the polyimide interlayer insulating film (5) is left until the end, so that in the past, the mask layer was removed separately. However, in the present invention, it is not necessary to remove the moisture-resistant insulating mask layer (6), and the process can be simplified.
また本発明に依れば、第２の配線層（９）のエツチング
に用いるホトレジスト層（１１）の除去に際し、ポリイ
ミド層間絶縁膜（５）の保護として働き、不要のポリイ
ミド層間絶縁膜（５）のエツチングを防止し、平坦な表
面の多層配線を実現できる。Further, according to the present invention, when removing the photoresist layer (11) used for etching the second wiring layer (9), the unnecessary polyimide interlayer insulating film (5) acts as a protector for the polyimide interlayer insulating film (5). It is possible to prevent etching and realize multilayer wiring with a flat surface.
更に本発明に依れば、耐湿性の劣るポリイミド層間絶縁
膜（５）上を耐湿性絶縁マスク層（６）で常に被覆して
いるので、製造中も製品化後も耐湿性の秀れた多層配線
の製造方法を実現できる。Furthermore, according to the present invention, the polyimide interlayer insulating film (5), which has poor moisture resistance, is always covered with the moisture-resistant insulating mask layer (6). A method for manufacturing multilayer wiring can be realized.
第１図Ａ乃至第１図Ｈは本発明の多層配線の製造方法を
説明する断面図、第２図Ａ乃至第２図Ｅは従来の多層配
線の製造方法を説明する断面図である。
（１）は半導体基板、 （２）は絶縁膜、 （３）は第
１の配線層、（４）は拡散領域、（５）はポリイミド層
間絶縁膜、 （６）は耐湿性絶縁マスク層、（７）はホ
トレジスト！、（８＞はコンタクト孔、（９）は第２の
配線層、 （１０）は金属層、 （１１）はホトレジス
ト層である。
出願人 三洋電機株式会社外１名
代理人 弁理士 西野卓嗣 外１名
第１ 図 八
第１図Ｂ
第１図Ｃ
第１図Ｄ
＠１図 Ｅ
第１図Ｆ
第１図Ｇ
第１図Ｈ
第２図へ
第２図Ｂ
第２図Ｃ1A to 1H are cross-sectional views illustrating the method of manufacturing a multilayer wiring according to the present invention, and FIGS. 2A to 2E are sectional views illustrating a conventional method of manufacturing a multilayer wiring. (1) is a semiconductor substrate, (2) is an insulating film, (3) is a first wiring layer, (4) is a diffusion region, (5) is a polyimide interlayer insulating film, (6) is a moisture-resistant insulating mask layer, (7) is photoresist! , (8> is a contact hole, (9) is a second wiring layer, (10) is a metal layer, and (11) is a photoresist layer. Applicant: Sanyo Electric Co., Ltd. and one other agent Patent attorney: Takuji Nishino 1 person 1 Figure 8 Figure 1 B Figure 1 C Figure 1 D @ Figure 1 E Figure 1 F Figure 1 G Figure 1 H Go to Figure 2 Figure 2 B Figure 2 C
Claims (1)
工程、前記第１の配線層を被覆するポリイミド層間絶縁
膜を付着し前記ポリイミド層間絶縁膜上を耐湿性絶縁マ
スク層で被覆する工程、前記耐湿性絶縁マスク層をホト
レジスト層で被覆し、所望のコンタクト孔を形成する部
分を露出する工程、前記耐湿性絶縁マスク層を前記ホト
レジスト層をマスクとして選択的にエッチングした後前
記ホトレジスト層を除去する工程、前記耐湿性絶縁マス
ク層をマスクとして前記ポリイミド層間絶縁膜をエッチ
ングし所望の前記第１の配線層上にコンタクト孔を形成
する工程、前記耐湿性絶縁マスク層上に第２の配線層と
なる金属層を被着し所望のパターンを有するホトレジス
ト層をマスクとして第２の配線層を形成する工程、前記
耐湿性絶縁マスク層で前記ポリイミド層間絶縁膜を保護
しながら前記ホトレジスト層を除去する工程とを有する
ことを特徴とする多層配線の製造方法。(1) Forming a first wiring layer on an insulating film of a semiconductor substrate, attaching a polyimide interlayer insulating film covering the first wiring layer, and covering the polyimide interlayer insulating film with a moisture-resistant insulating mask layer. a step of covering the moisture-resistant insulating mask layer with a photoresist layer and exposing a portion where a desired contact hole is to be formed; selectively etching the moisture-resistant insulating mask layer using the photoresist layer as a mask, and then etching the photoresist layer; a step of etching the polyimide interlayer insulating film using the moisture-resistant insulating mask layer as a mask to form a contact hole on the desired first wiring layer, and etching a second contact hole on the moisture-resistant insulating mask layer. forming a second wiring layer using a photoresist layer having a desired pattern as a mask; depositing a metal layer that will become a wiring layer; forming a second wiring layer while protecting the polyimide interlayer insulation film with the moisture-resistant insulation mask layer; 1. A method for manufacturing a multilayer wiring, comprising the step of removing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22000086A JPS6373648A (en) | 1986-09-17 | 1986-09-17 | Manufacture of multilayer interconnection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22000086A JPS6373648A (en) | 1986-09-17 | 1986-09-17 | Manufacture of multilayer interconnection |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6373648A true JPS6373648A (en) | 1988-04-04 |
Family
ID=16744360
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22000086A Pending JPS6373648A (en) | 1986-09-17 | 1986-09-17 | Manufacture of multilayer interconnection |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6373648A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5402683A (en) * | 1991-10-30 | 1995-04-04 | Toyota Jidosha Kabushiki Kaisha | Built-in amplifier-type combustion pressure sensor and manufacturing method thereof |
| JP2003124212A (en) * | 2001-10-09 | 2003-04-25 | Sanken Electric Co Ltd | Semiconductor device and its manufacturing method |
| JP2004186439A (en) * | 2002-12-03 | 2004-07-02 | Sanken Electric Co Ltd | Semiconductor device and method for manufacturing the same |
| JP2008177527A (en) * | 2006-12-19 | 2008-07-31 | Matsushita Electric Ind Co Ltd | Nitride semiconductor device |
| US8569843B2 (en) | 2008-10-21 | 2013-10-29 | Panasonic Corporation | Semiconductor device |
| US8748995B2 (en) | 2010-07-12 | 2014-06-10 | Panasonic Corporation | Nitride semiconductor device with metal layer formed on active region and coupled with electrode interconnect |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58219740A (en) * | 1982-06-16 | 1983-12-21 | Toshiba Corp | Semiconductor device |
| JPS6030153A (en) * | 1983-07-28 | 1985-02-15 | Toshiba Corp | Semiconductor device |
| JPS60103625A (en) * | 1983-11-11 | 1985-06-07 | Nec Corp | Semiconductor device |
| JPS6195553A (en) * | 1984-10-16 | 1986-05-14 | Matsushita Electric Ind Co Ltd | Multilayer wiring structure of semiconductor integrated circuit and manufacture thereof |
-
1986
- 1986-09-17 JP JP22000086A patent/JPS6373648A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58219740A (en) * | 1982-06-16 | 1983-12-21 | Toshiba Corp | Semiconductor device |
| JPS6030153A (en) * | 1983-07-28 | 1985-02-15 | Toshiba Corp | Semiconductor device |
| JPS60103625A (en) * | 1983-11-11 | 1985-06-07 | Nec Corp | Semiconductor device |
| JPS6195553A (en) * | 1984-10-16 | 1986-05-14 | Matsushita Electric Ind Co Ltd | Multilayer wiring structure of semiconductor integrated circuit and manufacture thereof |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5402683A (en) * | 1991-10-30 | 1995-04-04 | Toyota Jidosha Kabushiki Kaisha | Built-in amplifier-type combustion pressure sensor and manufacturing method thereof |
| JP2003124212A (en) * | 2001-10-09 | 2003-04-25 | Sanken Electric Co Ltd | Semiconductor device and its manufacturing method |
| JP2004186439A (en) * | 2002-12-03 | 2004-07-02 | Sanken Electric Co Ltd | Semiconductor device and method for manufacturing the same |
| JP2008177527A (en) * | 2006-12-19 | 2008-07-31 | Matsushita Electric Ind Co Ltd | Nitride semiconductor device |
| US8569843B2 (en) | 2008-10-21 | 2013-10-29 | Panasonic Corporation | Semiconductor device |
| US8748995B2 (en) | 2010-07-12 | 2014-06-10 | Panasonic Corporation | Nitride semiconductor device with metal layer formed on active region and coupled with electrode interconnect |
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