JPH03291936A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a good through-hole free from angular parts on the side wall, in an interlayer film on the lower wiring, by forming the through hole by anisotropic etching, and shaping an insulating layer by totally etching the insulating film after an etching mask is eliminated. CONSTITUTION:The following processes are included; a process wherein a first conducting layer 3 is formed on a semiconductor substrate 1, a process wherein an insulating layer 5 is formed on the whole surface so as to coat the layer 3, a process wherein an etching mask 6 having an aperture at a part above the layer 3 is formed on the layer 5, a process wherein the layer 5 of a specified depth under the aperture is eliminated by isotropic etching, a process wherein the layer 5 under the aperture is eliminated by anisotropic etching, a part of the surface of the first conducting layer 3 is exposed, and a through hole 8 is formed, a process wherein the etching mask 6 is eliminated and the whole surface of the insulating layer 5 is etched, and a process wherein a second conducting layer 7 electrically connected with the first conducting layer 3 via the through hole 8 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming multilayer wiring within a semiconductor device.

[Conventional technology]

As semiconductor devices become more highly integrated, it has become important to improve wiring technology as well as to miniaturize patterns. Multilayer wiring technology is a technology that supports this miniaturization of wiring.
This technology is currently used in many semiconductor devices.

FIG. 2 is a process cross-sectional view showing a conventional method for manufacturing multilayer wiring in a semiconductor device. In the figure, 1 is a silicon substrate, 2 is an oxide film, 3 is a first aluminum wiring, 4 is a resist, 5 is an oxide film, 6 is a resist, and 7 is a second aluminum wiring.

Next, the manufacturing method will be explained.

First, an oxide film 2 is formed on the semiconductor substrate 1 or a semiconductor element formed on the semiconductor substrate, and then an aluminum film is formed on the oxide film 2, and a resist 4 is formed by photolithography. Using this as a mask, the aluminum film is selectively removed to form the first aluminum wiring 3 (FIG. 2(a)).

Next, an oxide film 5 is deposited by CVD or the like so as to cover the oxide film 2 and the aluminum wiring 3 (see Fig. 2(b).
)).

Next, a resist 6 is formed by photolithography, and the upper part of the oxide film 5 is etched using an isotropic wet etching method. Because of the isotropic etching, a portion of the oxide film under the resist 6 is also removed, resulting in a shape as shown in FIG. 2(C).

Next, using the resist 6 as a mask, the oxide film 5 is etched using a reactive ion etching method to form a connection hole 8 (FIG. 2@).

Next, the resist 6 is removed, and a second aluminum wiring 7 is formed in the same manner as the first aluminum wiring 3, to obtain the structure shown in FIG. 2(e).

In the manner described above, multilayer wiring in a semiconductor device is formed.

[Problem to be solved by the invention]

However, since multilayer wiring in a conventional semiconductor device is formed through the steps described above, an angular portion A is formed on the side wall portion of the connection hole 8, as shown in FIG. 2(b). As a result, the aluminum wiring 7 covering the connection hole 8
When the aluminum wiring 7 is formed, the step coverage within the connection hole 8 is poor, which increases the resistance value and causes defects due to electromigration, etc.
There is a problem that the long-term reliability of the device deteriorates.

Furthermore, since the shape of the step coverage within the contact hole 8 of the aluminum wiring 7 tends to become a negative slope, the step coverage of the insulating film deposited on the aluminum wiring 7 deteriorates, and the insulating film is not filled into the contact hole. Enough to sing. As a result, if the purpose of the insulating film is a badge-beige tan film, moisture resistance to the semiconductor device becomes a problem, and if the insulating film is a glabellar insulating film, its flatness becomes a problem.

This invention was made in order to solve the above-mentioned problems in the prior art, and it is possible to form a good connection hole in the glabellar membrane on the lower layer wiring without having an angular part on its side wall. The purpose of the present invention is to provide a method for manufacturing a semiconductor device.

[Means to solve the problem]

A method for manufacturing a semiconductor device according to the present invention includes a step of forming a predetermined first conductive layer, a step of forming an insulating layer to cover the conductive layer, and a step of forming a first conductive layer on the insulating layer. forming an etching mask having an opening in the upper portion; and removing a portion of the insulating layer below the opening to a predetermined depth by performing isotropic etching; removing the insulating layer below the opening to expose a part of the surface of the conductive layer to form a contact hole; removing the etching mask; The method consists of a step of shaping the insulating layer by etching the entire surface of the insulating layer, and a step of forming a second conductive layer electrically connected to the first conductive layer through the connection hole. be.

[Effect]

In the present invention, the above-mentioned whole surface etching step rounds off the angular portions of the connection hole formed by the anisotropic etching in the previous step, thereby smoothing the shape of the connection hole.

〔Example〕

Hereinafter, a method for manufacturing a semiconductor device according to the present invention will be explained.

FIG. 1 is a cross-sectional view of each main process showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. In the figure, 1 is a silicon substrate, 2 is an oxide film, 3 is an aluminum wiring, 4
5 is a resist, 5 is an oxide film, 6 is a resist, 7 is an aluminum wiring, and 8' and 8 are connection holes.

The manufacturing method will be explained below.

First, an oxide film 2 is formed on a semiconductor substrate or a semiconductor element 1 formed on a semiconductor substrate. Next, an aluminum film is formed on the oxide film 2, and then a resist 4 is formed by photolithography. 4 as a mask, the aluminum film is selectively removed, and the first aluminum wiring 3 is removed.
form.

As a result, the structure shown in FIG. 1(a) is obtained.

Next, an oxide film 5 is deposited by CVD or the like so as to cover the oxide film 2 and the aluminum wiring 3, as shown in FIG. 1(b).
state. Here, this oxide film 5 is made thicker than the oxide film 5 formed in the step of FIG. 2(b) in the prior art.

Next, a resist 6 having openings is provided on the oxide film 5 by photolithography, and the upper part of the oxide film 5 is etched using an isotropic wet etching method. Due to isotropic etching, part of the oxide film under resist 6 is also removed.
A state as shown in FIG. 1(C) is obtained.

Next, using the resist 6 as a mask, a reactive ion etching method is used to remove the oxide film 5 and form a connection hole 8''.
Obtain the structure shown in figure (b).

Next, the resist 6 is removed and the entire surface is etched (anisotropically) to obtain a smooth connecting hole 8 as shown in FIG. 1(e).

Next, a second aluminum wiring layer is deposited on the oxide film 5 including the connection hole 8, a resist is patterned by photolithography, and the second aluminum wiring layer is selectively removed using this resist as a mask. Thereafter, the resist is removed to obtain seven layers of second aluminum wiring shown in FIG. 1(f).

When forming a third wiring layer from the state shown in FIG. 1(f), the top surface of the structure is covered with an insulating layer as shown in FIG. 1(f).
The steps shown in FIG. 1b) to (f) may be carried out below. At this time, the connection hole for connecting the second aluminum wiring 7 and the new third wiring layer may be provided above the connection hole 8 shown in FIG. They may be provided at different positions.

Furthermore, the present invention can be applied to the case of forming a connection hole for connecting a conductive layer such as a diffusion layer formed on a semiconductor substrate and a first wiring layer formed above the conductive layer.

Note that in the above embodiment, the wiring 3.7 is made of an aluminum film, but this may be made of an aluminum alloy (for example, AlSi, Al5iCu, Alcu, AIS iT
i, etc.), a high melting point metal, or even a laminated film of these materials.

Further, in the above embodiments, the insulating film is made of an oxide film, but it may be an insulating film made of a nitride film, an organic compound, or the like.

Furthermore, instead of the oxide film 5 in the above embodiment, it is also possible to form multilayered and various types of insulating films for the purpose of planarization.

〔Effect of the invention〕

As explained above, according to the present invention, the corners in the connection hole caused by anisotropic etching are formed by subsequent etching on the entire surface, so that the shape of the connection hole becomes smooth, and as a result, the upper layer This has the effect of improving step coverage within the connection hole of the wiring layer. Thereby, the reliability of the wiring can be improved and a semiconductor device with high reliability can be obtained.

[Brief explanation of drawings]

FIG. 1 is a process sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a process sectional view showing a conventional method for manufacturing a semiconductor device. In the figure, 1 is a semiconductor substrate, 2.5 is an oxide film, and 3.7
is an aluminum wiring, 4.6 is a resist, and 8.8° is a connection hole. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] (1) a step of forming a first conductive layer on a semiconductor substrate or a semiconductor layer; a step of forming an insulating layer over the entire surface so as to cover the conductive layer; and a step of forming an insulating layer on the insulating layer above the conductive layer. a step of forming an etching mask having an opening in a portion corresponding to the opening; a step of removing the insulating layer below the opening to a predetermined depth by performing isotropic etching; and anisotropic etching. removing the insulating layer below the opening and exposing a part of the surface of the first conductive layer to form a connection hole; removing the etching mask; Manufacturing a semiconductor device, comprising: etching the entire surface of the insulating layer; and forming a second conductive layer electrically connected to the first conductive layer through the contact hole. Method.