JPS6373634A - Method for inspection of semiconductor element - Google Patents

Abstract

PURPOSE:To simplify the work of characteristic inspection to be performed on a bipolar IC, to enhance the accuracy in measurement, and to improve the yield of production by a method wherein the collector layer of a semiconductor element and the scribe region which is the outer circumferential boundary of the element are short-circuited, the back surface of a semiconductor substrate is used as a collector electrode, and a measurement is performed using two measuring needles on the side of the surface of the substrate. CONSTITUTION:An oxide film 7 is removed in such a manner that the part, astriding the n<+> layer 5 which becomes a collector region and the scribe region A containing an isolation region 4, is exposed using photoresist technique for the purpose of emitter diffusion of a bipolar IC. Subsequently, SiO2 8 containing phosphorus oxide is deposited on the whole surface, and the n<+> diffusion layer 10, with which the collector n<+> layer 5 and the isolation p-layer 4 are short- circuited, is formed. The collector region 5 is electrically connected to the back surface of a wafer, and an hFE measurement can be performed by contacting two measuring needles for a base electrode and an emitter electrode on the wafer surface.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for testing semiconductor devices, and particularly to a technique for efficiently testing the electrical characteristics of ICs, LSIs, and the like including transistors.

[Prior art]

With the increasing integration of semiconductor integrated circuits such as ICs and LSIs,
As miniaturization is progressing at a rapid pace, evaluation and inspection technology in wafer processes has become important.

The evaluation items in this wafer process are cleaning, polishing, oxidation, diffusion, and microfabrication.

There are inspections of each process such as metallization, and finally electrical measurements of the basic elements as comprehensive characteristics (Kogyo Kenkyukai, Electronic Materials, August 1985, p. 23-25).

In particular, in TTL-IC, hFE4 of the transistor element
! In order to control the characteristics, inspection is performed after emitter diffusion, but the inspection method is more complicated than that for single transistors, which poses a problem.゛In other words, this is a technology being considered by the present inventors, which involves a test element provided at the end of a part of each pellet or as a part of a test pellet after emitter diffusion in the TTL-IC wafer process. That hi'l in a random inspection
By measuring the loft, control information for loft pass/fail and subsequent processing can be obtained.

One method is to use a semiconductor wafer 1 as shown in FIG.
collector n+ layer 5. which constitutes an npn) transistor which is an element for inspection on one main surface of the 5. Pace p layer6. Emitter n+
Each layer 9 is formed by diffusion, and after emitter diffusion,
A part of the phosphorus glass and oxide film (SiOm) 7 of the wafer containing the test element is removed by etching, and a measuring needle (CBE) is applied to each of the three regions of the collector, pace, and emitter.
) with a manipulator to measure hFI.

Another method, as shown in FIG. 9, is to remove only the phosphorus glass on the entire surface of the wafer, and use a phosphorus diffusion layer, which has also been formed in advance on a part of the paste region 6, as a paste electrode ω). hF with the B and C-B junctions protected by an oxide film.
Measure M.

[Problem that the invention seeks to solve]

In any of the above-mentioned methods, the measuring needles for the collector electrode are located on the wafer surface, that is, it is necessary to bring the three measuring needles into contact with the collector, pace, and emitter regions. These regions are small areas with a width of 20 to 30 μm at most, so contacting these areas with three needles at the same time requires skill and requires a large number of man-hours, and there is considerable variation in the measured characteristics, resulting in poor quality of the product. The yield was also low.

The present invention has been made to overcome the above-mentioned problems, and its purpose is to simplify the measurement work by reducing the number of stitches during measurement, and to improve measurement accuracy and yield.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a collector constitutes a semiconductor element for inspection on a part of the main surface of a semiconductor substrate (wafer).

When forming the paste and emitter diffusion layers and contacting each region with a measuring needle to measure the electrical characteristics of the element,
The collector layer of the element is short-circuited to the scribe area, which is the outer peripheral boundary of the element, and the back surface of the semiconductor substrate is used as a collector electrode, and the measurement is performed using two measuring needles on the front surface side.

[Effect]

According to the above-mentioned means, by using the back surface of the substrate as a collector electrode, measurement can be performed using two needles on the top surface, which simplifies the work, prevents a decrease in measurement accuracy, and can be expected to improve yield.

〔Example〕

FIGS. 1 to 4 show an embodiment of the present invention, in which cross-sections of main steps of a process in which npn) transistors are released on the whole surface of a semiconductor wafer and their characteristics are inspected in bipolar ICE. It is a diagram.

The following description will be made in accordance with the order of the steps with reference to the drawings.

(13 Following the normal bi-bo 2 IC process, the first
As shown in the figure, an epitaxial n'''' Si layer is formed on a part of the whole surface of a p'''' Si substrate 1 through an n+ buried layer 2, and one layer surrounded by an isolation layer 1 and a p layer 4 is formed. Using the island region as one semiconductor element region, a collector extraction n+ diffusion layer 5 is formed, and then a pace p diffusion layer 6 is formed. The semiconductor element shown in the figure is used as a characteristic testing element (TEG), and one TEG is provided for each semiconductor pellet close to a scribe region that is a boundary between the semiconductor pellets.

(2) When removing a part of the oxidized layer 7 on the surface by photofusing technology for emitter diffusion, as shown in FIG. The oxide film 7 is removed so that a portion extending over a large scribe region including the oxide film 7 is exposed.

(31 After this, S iol s containing phosphorus oxide on the entire surface
A so-called phosphorus glass 8 is deposited, phosphorus is diffused into the exposed portion of Si, and an emitter n is formed as shown in FIG.
+At the same time as forming the diffusion layer 9, an n diffusion layer 10 is formed to short-circuit the collector n layer 5 and the isolation layer 4.

Emitter diffusion methods generally include POC, I3. A carrier gas is used, and in this case, as shown in FIG. 5, an n+ diffusion layer 10 made of the same impurity as the emitter is formed on both the front and back surfaces of the wafer. The TEG is formed close to the scribe area A as shown in FIG. 6 or 7, and this scribe area extends to the wafer periphery, so that the collector area 5 of the TEG is an n+ diffused scribe. It will be electrically connected to the backside of the wafer through the region.

(41) Therefore, when testing the characteristics after emitter diffusion, as shown in Fig. Then pace electrode 0
3) and the emitter electrode (p), hF1 measurement becomes possible.

Conventional bipolar ICs use three measuring needles, each requiring independent manibrator operation, but as described above, the present invention uses two measuring needles to simplify the work. Furthermore, by combining two needles and adjusting the distance between the tips of the needles, it is possible to form a single manipulator, and automation of measurement is also possible.

According to the present invention, it is possible to prevent a decrease in measurement accuracy due to insufficient contact adjustment of the needle during measurement, that is, an increase in hFE defects, and as a result, it is expected to reduce characteristic variations and improve yield. Note that short-circuiting between the collector region and the scribe region can be accomplished by simply changing a part of the mask and using emitter diffusion as is, without changing or increasing the number of steps.

Although the invention made by the present inventor has been specifically explained based on examples, the present invention is not limited to the above-mentioned examples, and various changes can be made without departing from the gist of the invention. It's no good.

The most effective product to which this invention is applied is LS-'ITL.

These are digital IC's such as 5-TTL and N-TTL.

The present invention can also be applied to linear ICs that are other semiconductor products.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, it is possible to simplify the work in testing the characteristics of bipolar ICs, improve measurement accuracy, and improve yield.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 to 4 show an embodiment of the present invention, and are cross-sectional views of steps (including inspection steps) in a bipolar IC manufacturing process. FIG. 5 is a cross-sectional view showing the formation of the n-diffusion layer along the scribe region. FIGS. 6 and 7 are plan views showing the positional relationship between the scribe area and the TEG in each of the upper bullets. FIG. 8 and FIG. 9 are cross-sectional views showing conventional examples of characteristic testing methods for bipolar ICs. 1... p-3i substrate (wafer), 2... n+ buried layer, 3... epitaxial n"'5iffi, 4...
Ainlation p layer, 5... Collector n+ diffusion layer,
6...Pace p diffusion layer, 7...Oxide film, 8...Phosphorous glass, 9...Emitter n+diffusion layer, 10...n
10 diffusion layer, A... scribe area. Agent: Patent Attorney Katsuo Ogawa, 4th
Figure 5 Figure 6 Figure 7

Claims (1)

[Claims] 1. A collector layer, a base layer, and an emitter layer constituting a bipolar semiconductor element are formed on a part of one main surface of a semiconductor substrate by diffusion, and a measuring needle is brought into contact with the surface of each region. A semiconductor device characterized in that, in measuring the electrical characteristics of a semiconductor device, the collector layer of the device is short-circuited to a scribe region that is a boundary between the devices, and the measurement is performed using the back side of the semiconductor substrate as a collector electrode. testing method. 2. The method for inspecting a semiconductor device according to claim 1, wherein the short circuit between the collector layer and the scribe region of the semiconductor device is achieved by diffusing impurities at a high concentration so as to straddle the two regions during emitter diffusion.