JPS61269324A - Semiconductor device - Google Patents

Abstract

PURPOSE:To measure and evaluate pickup resistance values at every chip quantatively by using a region consisting of two adjacent epitaxial-silicon layers as a P-type pickup region from a substrate and connecting the region by a P-type buried layer. CONSTITUTION:N<+> type introduction layers 12 and a P<+> type introduction layer 13 are formed to a P<-> type Si substrate 11. Si is grown on the whole surface in an epitaxial manner to shape an N<-> type Si layer 14 in low concentration. The surface of the Si layer is oxidized selectively to form oxide films 17 for isolation so as to reach buried layers 12, 13. P-type diffusion layers 19 are connected to the P-type buried layer 13. Electrodes 20 are employed as electrodes for a monitor element for measuring the resistance of lifting sections from the substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a technique for measuring the resistance of a pulled-up portion of a substrate in a semiconductor device, particularly in a semiconductor integrated circuit using an oxide film separation method.

[Background technology]

Isolation (element isolation) for semiconductor integrated circuits (ICs) has changed from conventional pn junction isolation to oxide film isolation in current LSIs.

In oxide film isolation, by using an insulating material such as a semiconductor oxide for the isolation region, poor isolation caused by the entry of depletion layers can be countered, and the minimum isolation width can be obtained in the lateral direction, reducing the isolation area and allowing for high integration. It becomes possible to

(Published by Kogyo Kenkyukai, "Electronic Materials" magazine, July 1982 issue, Pill) When manufacturing bipolar ICs using the oxide film separation process, a diffusion layer called a channel stopper is used to increase the threshold voltage of the parasitic N-channel MO8FET. The part directly under the oxidation separation film (the same P-type layer as the substrate)
There are two methods for manufacturing it, a reach-down method and a reach-up method. The reach-down method is a method in which P-type impurity atoms are introduced from the surface of the NFI epitaxial Si layer on the P-type substrate to form a channel stopper, and the reach-up method is a method in which P-type impurity atoms are introduced from the surface of the NFI epitaxial Si layer on the P-type substrate to form a channel stopper. This is a method in which P-type impurity atoms are introduced into the region in advance and are caused to rise upward simultaneously with the growth of the n-type epitaxial Si layer.

The applicants of the present application have developed a process for forming a channel stopper by adopting a reach-up method when forming an ultra-high-speed bipolar IC, such as an emitter-coupled logic (ECL).

FIG. 9 shows a device structure (hereinafter, this portion will be referred to as a pull-up portion) for bringing a substrate to a ground potential, which was developed by the applicant of the present invention prior to the present invention. That is, in the same figure, 1 is a P-type 8i substrate (substrate), 2 is an n+ type buried layer, 3 is a P+ buried layer, 4 is an epitaxially grown Si layer, and 4 is a diffusion layer from above and a bottom layer. This is a raised portion P type layer formed by upward diffusion from the P+ type buried layer 3.

5 is an isolation oxide film, 6 is an n+ layer (CN) for taking out the collector of the npn transistor, 7 is a base P type layer, and 8 is an emitter n+ grave layer. The P-type layer 4' is formed in the same process as the PW layer 7.

In such a structure, the impurity concentration profile of the above-mentioned pull-up section A-A' is as shown in Fig. 10. Since there are some low-concentration parts, the pull-up resistance R across the substrate can become large. However, it was found that the voltage drop across the resistor hole caused the substrate potential to rise slightly above the ground potential, making it impossible to obtain good isolation and device characteristics. In other words, it has been found that the resistance hole value is an extremely important value for detecting defects in semiconductor devices.

However, in the conventional structure, there is no means to quantitatively monitor the value of the resistance hole, and due to the occurrence of defects in finished products, the yield is low and cost reductions cannot be achieved.

[Purpose of the invention]

The present invention has been made to overcome the above-mentioned problems, and its object is to provide a structure of a semiconductor device that makes it possible to monitor the pulling resistance across a substrate.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in a semiconductor device, an epitaxial silicon layer is grown on a P-type silicon substrate, a separation layer made of a silicon oxide film is formed on the surface of this silicon layer, and a P-type layer is formed under this oxide film separation layer. , the above oxide film and P
A region consisting of two epitaxial silicon layers separated by a mold layer is used as a P-type pull-up region from the substrate, and these two P-type regions are connected by a P-type buried layer formed directly under the oxide film. Therefore, it is used as a monitor for measuring pulling resistance, and thereby,
It has become possible to quantitatively measure and evaluate the pulling resistance value of each chip.

〔Example〕

FIGS. 1 to 6 show an embodiment of the present invention, and are cross-sectional views of a process for forming a monitor element for measuring pulling resistance.

The process for forming a monitor for resistance measurement will be explained in the order of steps below.

(1) In the P- type 8i substrate 11, using an oxide film (not shown) using photoresist as a mask, impurities such as KSb and B are sequentially introduced to form the buried layer to form the n+ type introduced layer 12 and the P+ type. A mold introduction layer 13 is formed.

(FIG. 1) (2) Si is epitaxially grown on the entire surface to form a low concentration n-type Si layer 14 with a thickness of about 1 to 2 μm.

As a result, the impurity-introduced layer is buried to become an n+ type buried layer 12 and a P+ type buried layer 13. (Fig. 2) (3) Si oxide film (Sin), nitride film (SisN4)
), and the surface of the 81 layer 14 is partially etched to form a groove 16. (FIG. 3) (4) Using the mask 15, the surface of the Si layer is selectively oxidized to form an isolation oxide film 17 so as to reach the buried layers 12 and 13. Next, an n-type layer 24 that will become the collector of the NPN transistor is formed. (Figure 4) (5) Boron B is ion-implanted or diffused using a high-pressure, low-temperature deposited oxide film 18 (a photoresist film may be used) as a mask to convert the P-type diffused layer 19 into a P-type buried layer. 13. This ion implantation process may be an ion implantation process for forming the base 22 of an NPN transistor. By doing so, it can be formed without increasing the number of steps. (5th
(6) After contact photoetching is performed on the oxide film formed on the surface of the P-type layer 19 to form the emitter part 23 of the NPN transistor, the oxide film on the electrode part is selectively removed and the AI AJ is deposited using photoresist.
Patterning is performed to form electrodes 20, and a monitor element for measuring the resistance of the raised portion of the substrate is completed. (6th
FIG. 7 is a plan view showing the positions of the P diffused layer and the P+ type buried layer, and FIG. 6 corresponds to the AA' cross section in FIG. 7.

FIG. 8 is an overall plan view showing the monitor element part in one chip 21, and the blank part of the figure is an IC, L
Elements such as SI are formed.

〔Effect of the invention〕

According to the present invention described in the above embodiments, the following effects can be obtained.

The measurement of the pulling resistance across the substrate using the monitor element is performed as follows.

For the resistance value of the monitor element, refer to FIGS. 6 and 7. R=几, 10B! +Rs (R+ =Rs)
=21. +Rt (However, PSub up is the specific resistance of the substrate pulling part A8
ub is the area of the substrate pulling part Ppiso is the specific resistance of piso) Here, Psub up is determined by the BR (P type diffusion base) concentration, the thickness of the epitaxial layer, etc. Therefore, if the measurement result does not satisfy a certain standard value, it can be seen that the substrate has not been lifted up enough and the chip or wafer is defective.

By quantitatively measuring and evaluating the resistance value R using a monitor element in this way, it is possible to identify chips with abnormally large input latch-up %IEE due to large substrate pulling resistance or insufficient channel stopper concentration. It becomes possible to eliminate wafer products.

Therefore, according to the present invention, although the wafer completion yield or pellet inspection yield decreases by utilizing the monitor element, it is possible to prevent the occurrence of defects in finished products and reduce the total cost by about 10%. becomes possible.

[Application field]

The present invention can be applied to all semiconductor devices (IC, LSI) that employ a reach-up method in an oxidation separation process.

In addition to the above, the present invention can be applied to general semiconductor products in which the resistance of the substrate is taken out from the P+ type buried layer.

[Brief explanation of drawings]

FIGS. 1 to 6 are cross-sectional views of a manufacturing process of a monitor for measuring substrate pulling resistance according to an embodiment of the present invention. FIG. 7 is a plan view corresponding to FIG. 6. FIG. 8 is an overall plan view showing an example of the position of the monitor element on the chip. FIG. 9 is a sectional view showing an example of a conventional substrate lifting section. FIG. 10 is a curve diagram of the surface impurity profile of the section AA' in FIG. 11...P- type Si substrate, 12...n-type buried layer,
13...P+ type buried layer, 14...Epitaxial S
i layer, 15... mask, 16... groove, 17...
Isolation oxide film, 18...mask% 19...P diffusion layer, 20...AI! Electrode, 21...chip. Figure 1 Figure 2 Figure 3 Figure 7 Figure 8

Claims (1)

[Claims] 1. A first conductivity type semiconductor substrate, a semiconductor layer epitaxially grown on one main surface of this semiconductor substrate, an isolation oxide film partially formed on the surface of this semiconductor layer, and this isolation A semiconductor device comprising a first conductivity type buried layer formed between an isolation oxide film and a semiconductor substrate, the epitaxial semiconductor region being separated by the isolation oxide film and the first conductivity type buried layer. Two of the adjacent semiconductor regions are used as first conductivity type regions, and these are electrically connected by a first conductivity type buried layer formed under the isolation oxide film between them, thereby serving as a monitor for measuring the resistance of the upper part pulled up from the substrate. A semiconductor device characterized by: 2. The semiconductor device according to claim 1, wherein the lower part of the first conductivity type epitaxial semiconductor region is made into a first conductivity type layer by upward diffusion from the first conductivity type buried layer.