JPS6362369A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6362369A JPS6362369A JP20815486A JP20815486A JPS6362369A JP S6362369 A JPS6362369 A JP S6362369A JP 20815486 A JP20815486 A JP 20815486A JP 20815486 A JP20815486 A JP 20815486A JP S6362369 A JPS6362369 A JP S6362369A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- polycide
- electrode
- channel mos
- field effect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 23
- 230000005669 field effect Effects 0.000 claims abstract description 24
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 22
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 16
- 239000007772 electrode material Substances 0.000 claims abstract description 11
- 238000009792 diffusion process Methods 0.000 claims description 36
- 238000002844 melting Methods 0.000 claims description 11
- 230000008018 melting Effects 0.000 claims description 8
- 230000004888 barrier function Effects 0.000 claims description 5
- 239000003870 refractory metal Substances 0.000 claims description 5
- 229910052723 transition metal Inorganic materials 0.000 claims description 4
- 150000003624 transition metals Chemical class 0.000 claims description 4
- 230000005684 electric field Effects 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 21
- 229920005591 polysilicon Polymers 0.000 abstract description 21
- 238000006243 chemical reaction Methods 0.000 abstract description 8
- 230000002542 deteriorative effect Effects 0.000 abstract description 5
- 238000000605 extraction Methods 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 239000005360 phosphosilicate glass Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- PRESPHWJFNSVAB-UHFFFAOYSA-N [Ti].[Ni].[Sn] Chemical compound [Ti].[Ni].[Sn] PRESPHWJFNSVAB-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明が解決しようとする問題点〕
本発明は、半導体装置に関し、特にＮＰＮバイポーラ・
トランジスタと導電形を異にするＰチャネルおよびＮチ
ャネル２種類のＭＯＳ電界効果トランジスタとが互いに
混在する半導体装置の取出電極の構造に関する。[Detailed Description of the Invention] [Problems to be Solved by the Invention] The present invention relates to a semiconductor device, and in particular to an NPN bipolar device.
The present invention relates to a structure of an extraction electrode of a semiconductor device in which two types of P-channel and N-channel MOS field effect transistors having different conductivity types coexist with each other.
従来、パイ・モス（Ｂｉ−ＭＯＳ）と呼ばれるこの種半
導体装置の電極は、Ｎ膨拡散層との間にはＮ形のポリシ
リコン層を、また、Ｐ形波散層との間にはＰ形のポリシ
リコン層をそれぞれ介在させ拡散層内へ電極材の拡散を
この介在層により抑え込む取出構造が一般に採用される
。Conventionally, the electrode of this type of semiconductor device called Bi-MOS has an N-type polysilicon layer between it and the N-swelling diffusion layer, and a P-type polysilicon layer between it and the P-type wave diffusion layer. Generally, a lead-out structure is adopted in which a polysilicon layer of a shape is interposed between the electrodes and the diffusion of the electrode material into the diffusion layer is suppressed by the intervening layer.
第３図は従来のパイ・モス（Ｂｉ−ＭＯＳ）半導体装置
の断面構造図で、上記の電極構造を詳細に示したもので
ある。第３図によれば、Ｐ形半導体基板１のＮウェル２
内にはソース領域３．ドレイン領域４およびシリコン・
ゲート電極５から成るＰチャネルＭＯＳ電界効果トラン
ジスタが、また、Ｐウェル６内にはソース領域７．ドレ
イン領域８およびシリコン・ゲート電極９から成るＮチ
ャネルＭＯＳ電界効果トランジスタがそれぞれ形成され
、更にこれと隣接してＮ−およびＮ１形コレクタ領域１
０および１１．ベース領域１２およびエミッタ領域１３
から成るＮＰＮバイポーラ・トランジスタが形成され、
それらの取出電極と各拡散領域との接触部分には拡散領
域の導電形に應しこれと等しい導電形のＮ形またはＰ形
のポリシリコン層がそれぞれ介在される。すなわち、Ｐ
チャネルＭＯＳ電界効果トランジスタのソース、ドレイ
ン電極１４ａ、１４ｂの接触部分にはソース。FIG. 3 is a cross-sectional structural diagram of a conventional Bi-MOS semiconductor device, showing the above-mentioned electrode structure in detail. According to FIG. 3, an N-well 2 of a P-type semiconductor substrate 1
Inside is the source area 3. Drain region 4 and silicon
A P-channel MOS field effect transistor consisting of a gate electrode 5 and a source region 7 . N-channel MOS field effect transistors are formed, each consisting of a drain region 8 and a silicon gate electrode 9, and further adjacent N- and N1 type collector regions 1.
0 and 11. Base region 12 and emitter region 13
An NPN bipolar transistor is formed consisting of
At the contact portions between these extraction electrodes and each diffusion region, an N-type or P-type polysilicon layer having the same conductivity type as that of the diffusion region is interposed. That is, P
A source is provided at the contact portion of the source and drain electrodes 14a and 14b of the channel MOS field effect transistor.
ドレイン領域３，４のＰ′″拡散層に合わせてＰ形ポリ
シリコン層１７がそれぞれ介在され、また、Ｎチャネル
ＭＯＳ電界効果トランジスタのソース。A P-type polysilicon layer 17 is interposed to match the P'' diffusion layers of the drain regions 3 and 4, and also serves as the source of the N-channel MOS field effect transistor.
ドレイン電極１５ａ、ｉ５ｂの接触部分にはソース、ド
レイン領域７，８のｎ＋拡散層に合わせてＮ形ポリシリ
コン層１８がそれぞれ介在される。N-type polysilicon layers 18 are interposed at the contact portions of the drain electrodes 15a and i5b, corresponding to the n+ diffusion layers of the source and drain regions 7 and 8, respectively.
更にＮＰＮバイポーラ・トランジスタのベース電極１６
ａ、エミッタ電極１６ｂ、コレクタ電極１６ｃの各接触
部分に対しても全く同様にしてＰ形ポリシリコン層１７
またはＮ形ポリシリコン層１８が下部拡散層の導電形に
応じてそれぞれ介在される。なお、１９および２０は厚
膜のフィールド絶縁膜およびリン硅酸ガラス膜（ＰＳＧ
）をそれぞれ示すものである。Furthermore, the base electrode 16 of the NPN bipolar transistor
P-type polysilicon layer 17 is applied to each contact portion of a, emitter electrode 16b, and collector electrode 16c in exactly the same manner.
Alternatively, an N-type polysilicon layer 18 is interposed depending on the conductivity type of the lower diffusion layer. Note that 19 and 20 are thick field insulating films and phosphosilicate glass films (PSG).
) respectively.
しかしながら、この従来の電ｉ構造では、電極の金属材
が下部の拡散層内に拡散することは防止できるものの他
方では電極材が介在させたポリシリコン層と化学反応し
て、シリコンを析出せしめ電極すなわち配線寿命を短縮
して半導体装置の信頼性を著しく低下させる場合が生じ
る。また、バイポーラ・トランジスタのベース抵抗はポ
リシリコン層を介する分だけ高くなるので素子の高速化
に対して障害を与えるようになる。このような電極材と
ポリシリコン層との反応を抑えるにはそれぞれの接触部
をシリサイド化すれば良いが、バイポーラ・トランジス
タのエミッタ領域およびＮチャネルＭＯＳ電界効果トラ
ンジスタのソース、ドレイン領域は高速化を目的として
微細化され、特に拡散層が浅く形成されるので取出電極
との接触部をシリサイド化すると素子特性を劣化させる
という新たな問題を生じる０以上は特にパイ・モス（Ｂ
ｉ−ＭＯＳ）半導体装置について述べたが浅い拡散層を
有する半導体装置では共通した問題点として常に存在す
る。However, in this conventional electrical structure, although it is possible to prevent the metal material of the electrode from diffusing into the diffusion layer below, on the other hand, the electrode material chemically reacts with the intervening polysilicon layer to precipitate silicon, causing the electrode to In other words, the life of the wiring may be shortened and the reliability of the semiconductor device may be significantly lowered. Furthermore, the base resistance of the bipolar transistor increases due to the presence of the polysilicon layer, which poses an obstacle to increasing the speed of the device. In order to suppress such a reaction between the electrode material and the polysilicon layer, each contact part can be silicided, but the emitter region of a bipolar transistor and the source and drain regions of an N-channel MOS field effect transistor need to be formed at higher speeds. Since the purpose of miniaturization is to form a shallow diffusion layer, silicide of the contact part with the extraction electrode causes a new problem of deteriorating the device characteristics.
Although the i-MOS) semiconductor device has been described above, this problem always exists as a common problem in semiconductor devices having a shallow diffusion layer.
本発明の目的は、上記の情況に鑑み、浅い拡散層との接
触部におけるポリシリコン層との反応を素子特性を劣化
せしめることなく有効に抑止することのできる取出電極
構造を備えた半導体装置を提供することである。In view of the above circumstances, an object of the present invention is to provide a semiconductor device equipped with an extraction electrode structure that can effectively suppress reactions with a polysilicon layer at a contact portion with a shallow diffusion layer without deteriorating device characteristics. It is to provide.
本発明によれば半導体装置は、ｎ＋エミッタ拡散層およ
びＰ形ベース拡散層との接触部分にはそれぞれ高融点金
属のポリサイド層およびシリサイド層を、またｎ＋コレ
クタ拡散層との接触部分には高融点金属のポリサイド層
またはシリサイド層をそれぞれ介在せしめる取出電極を
備えるＮＰＮバイポーラ・トランジスタを含み、またｎ
＋エミッタ拡散層およびＮチャネルＭＯ５ＩＥ界効果ト
ランジスタのｎ＋ソース、ドレイン拡散層との接触部分
にはそれぞれ高融点金属のポリサイド層を、またＰ形ベ
ース拡散層およびＰチャネルＭＯＳ電界トランジスタの
Ｐ＋ソース、トレイン拡散層との接触部分には高融点金
属のシリサイド層を、更にｎ＋コレクタ拡散層との接触
部分には高融点金属のポリサイド層またはシリサイド層
をそれぞれ介在せしめる取出電極を備えるＮＰＮバイポ
ーラ・トランジスタ、ＮチャネルＭＯＳ電界効果トラン
ジスタおよびＰチャネルＭＯＳ電界効果トランジスタと
を含んでパイ・モス（Ｂｉ−ＭＯＳ）１成とされ、更に
、前記高融点金属のポリサイド層またはシリサイド層と
電極材との間に前記電極材の遷移金属からなるバリア層
を付加形成される場合を含んでそれぞれ構成される。According to the present invention, the semiconductor device includes a polycide layer and a silicide layer of high melting point metal in the contact portions with the n+ emitter diffusion layer and the P type base diffusion layer, respectively, and a high melting point metal polycide layer and silicide layer in the contact portion with the n+ collector diffusion layer. It includes an NPN bipolar transistor equipped with an extraction electrode in which a metal polycide layer or silicide layer is interposed, respectively;
A polycide layer of a refractory metal is applied to the contact portions of the + emitter diffusion layer and the n+ source and drain diffusion layers of the N-channel MO5IE field effect transistor, and the P-type base diffusion layer and the P+ source and train of the P-channel MOS field effect transistor. NPN bipolar transistor, NPN bipolar transistor, equipped with an extraction electrode in which a silicide layer of a refractory metal is interposed in a contact portion with the diffusion layer, and a polycide layer or a silicide layer of a refractory metal is interposed in a contact portion with the n+ collector diffusion layer, respectively; A Bi-MOS (Bi-MOS) single structure is formed including a channel MOS field effect transistor and a P channel MOS field effect transistor, and the electrode is further provided between the polycide layer or silicide layer of the refractory metal and the electrode material. Each structure includes a case where a barrier layer made of a transition metal is additionally formed.
以下図面を参照して本発明の詳細な説明する。 The present invention will be described in detail below with reference to the drawings.
第１図は本発明の一実施例を示す半導体装置の断面図で
、ＮおよびＰの各チャネルＭＯＳ電界効果トランジスタ
とＮＰＮバイポーラ・トランジスタとを含むパイ・モス
（Ｂ １−ＭＯＳ ） ８４成に実施した場合を示すも
のである。本実施例によれば、本発明の半導体装置は、
Ｐ形半導体基板１と、Ｎウェル２内に形成されたＰ＋拡
散層のソースおよびドレイン領域３および４．シリコン
・ゲート電極５および高融点金属（例えばタングステン
）のシリサイド層２１を介してそれぞれ引出されたソー
スおよびドレインの各取出電極１４ａ、１４ｂとを備え
るＰチャネルＭＯＳ電界効果トランジスタと、Ｐウェル
６内に形成されなＰ＋拡散層のソースおよびドレイン領
域７および８．シリコン・ゲート電極９および高融点金
属のポリサイド層２２を介してそれぞれ引出されたソー
スおよびドレインの各取出電極１５ａおよび１５ｂを備
えるＮチャネルＭＯ９ｔＪ界効果トランジスタと、Ｎ形
およびＮ形コレクタ領域１０および１１．Ｐ形ベース領
域１２．ｎ＋エミッタ電極１６ｂ、コレクタ電極１６ｃ
を備えるＮＰＮバイポーラ・トランジスタとを含む。こ
こで、１９は厚膜フィールド絶縁膜、２０はリン硅酸ガ
ラス層、２３はＣＶＤシリコン酸化膜である。FIG. 1 is a cross-sectional view of a semiconductor device showing an embodiment of the present invention, which is implemented in a 84-channel PMOS (B1-MOS) structure including N and P channel MOS field effect transistors and an NPN bipolar transistor. This shows the case where According to this embodiment, the semiconductor device of the present invention is
A P type semiconductor substrate 1 and source and drain regions 3 and 4 of a P+ diffusion layer formed in an N well 2. A P-channel MOS field effect transistor is provided with a silicon gate electrode 5 and source and drain extraction electrodes 14a and 14b respectively drawn out through a silicide layer 21 of a high melting point metal (for example, tungsten), and a P-channel MOS field effect transistor in a P well 6. Source and drain regions 7 and 8 of unformed P+ diffusion layers. An N-channel MO9tJ field-effect transistor comprising source and drain extraction electrodes 15a and 15b respectively drawn out through a silicon gate electrode 9 and a polycide layer 22 of high-melting point metal, and N-type and N-type collector regions 10 and 11. ．． P-shaped base region 12. n+ emitter electrode 16b, collector electrode 16c
and an NPN bipolar transistor. Here, 19 is a thick field insulating film, 20 is a phosphosilicate glass layer, and 23 is a CVD silicon oxide film.
本実施例の半導体装置は次の順序工程図で容易に製造し
得る。すなわちＮチャネルとＰチャネルの各ＭＯＳ電界
効果トランジスタのソース、ドレイン３，４，７．８お
よびＮＰＮバイポーラ・トランジスタのベース領域１２
．コレクタ領域１１をそれぞれ形成した後ＣＶＤシリコ
ン酸化膜２３を３０００人成長させ、ついでバイポーラ
・トランジスタのエミッタ部およびＮチャネルＭＯＳ電
界効果トランジスタのソース、ドレイン部をそれぞれ開
口する。ここでポリシリコンを２５００人成長させ、前
記開口部以外のポリシリコンを除去した後、砒素（Ａ、
）を全面にイオン注入する。The semiconductor device of this example can be easily manufactured using the following sequential process diagram. namely, the source, drain 3, 4, 7.8 of each N-channel and P-channel MOS field effect transistor and the base region 12 of the NPN bipolar transistor.
．． After forming the collector regions 11, 3000 CVD silicon oxide films 23 are grown, and then the emitter portion of the bipolar transistor and the source and drain portions of the N-channel MOS field effect transistor are opened. Here, 2,500 polysilicon layers were grown, and after removing the polysilicon area other than the opening, arsenic (A,
) is ion-implanted over the entire surface.
ついで熱処理を行ない、エミッタ領域１３を形成した後
リン硅酸ガラス膜（ＰＳＧ）２０を成長させ、リフロー
後、各トランジスタとのコンタクト孔をそれぞれ開口し
更に開口部のポリシリコンおよびシリコンを、例えば、
タングステン・シリサイドまたはポリサイドにそれぞれ
変換した後アルミニウムを金属層的０．６μｍ被着して
所定の電極パターンを形成すればよい。Then, heat treatment is performed to form an emitter region 13, a phosphosilicate glass film (PSG) 20 is grown, and after reflow, contact holes for each transistor are opened, and the polysilicon and silicon in the openings are removed, for example.
After converting into tungsten silicide or polycide, a metal layer of aluminum of 0.6 μm is deposited to form a predetermined electrode pattern.
本実施例によれば、浅いｎ＋エミッタ領域１３およびＮ
チャネルＭＯＳ電界効果トランジスタの同じく浅いソー
ス、ドレイン領域７．８の取出電極はそれぞれポリサイ
ド層２２を介して引出され、その他の深い拡散領域の取
出電極にはシリサイド層２１がそれぞれ介在される。こ
のように浅い拡散層にポリサイド層が形成された場合は
シリサイド層の如く拡散層表面を傷めないので電極材と
ポリシリコン層との化学反応を素子特性を劣化すること
なく有効に阻止せしめることが可能である。According to this embodiment, the shallow n+ emitter region 13 and the N+
The lead electrodes of the similarly shallow source and drain regions 7.8 of the channel MOS field effect transistor are each led out through a polycide layer 22, and the lead electrodes of the other deep diffusion regions are each interposed with a silicide layer 21. When a polycide layer is formed in a shallow diffusion layer like this, unlike a silicide layer, it does not damage the surface of the diffusion layer, so it is possible to effectively prevent the chemical reaction between the electrode material and the polysilicon layer without deteriorating the device characteristics. It is possible.
以上はパイ・モス（Ｂｉ−ＭＯＳ）構成の場合を説明し
たが、勿論ＮＰＮバイポーラ・トランジスタまたはＮチ
ャネルＭＯＳ電界効果トランジスタ単独について実施し
得ることも明らかである。Although the case of the Bi-MOS (Bi-MOS) configuration has been described above, it is obvious that the present invention can also be implemented with an NPN bipolar transistor or an N-channel MOS field effect transistor alone.
また、この場合コレクタ領域１１からの引出しにはポリ
サイド層２２に変えてシリサイド層２１を介在させても
よい、何故なら拡散層１１が深いからである。Further, in this case, a silicide layer 21 may be interposed in place of the polycide layer 22 for leading out from the collector region 11, since the diffusion layer 11 is deep.
なお、電極材（アルミ）とポリサイド層２２またはシリ
サイド層２１との間で稀に反応が生じることがあるが、
そのような場合は更にチタン・ニッケル（ＴｉＮ）の如
き遷移金属をバリヤとして両者の間に介在せしめればよ
い。Note that in rare cases a reaction may occur between the electrode material (aluminum) and the polycide layer 22 or silicide layer 21;
In such a case, a transition metal such as titanium-nickel (TiN) may be interposed between the two as a barrier.
第２図は本発明の他の実施例を示す半導体装置の断面図
で、取出電極１４ａ、１４ｂ、１５ａ。FIG. 2 is a sectional view of a semiconductor device showing another embodiment of the present invention, showing extraction electrodes 14a, 14b, and 15a.
１５ｂ、１６ａ、１６ｂ、１６ｃとシリサイド層２１ま
たはポリサイド層２２との間にチタン・ニッケル（Ｔｉ
Ｎ）層のバリア層２４を付加形成したもので、上記反応
の発生を阻止せしめたものである。Titanium/nickel (Ti
A barrier layer 24 (N) layer is additionally formed to prevent the above reaction from occurring.
以上詳細に説明したように、本発明によれば、浅い拡散
層をもつＮＰＮバイポーラ・トランジスタまたはＮチャ
ネルＭＯＳ電界効果トランジスタの素子特性を劣化せし
めることなく、電極材とポリシリコン層との反応をきわ
めて有効に阻止し得るので、電極寿命すなわち配線寿命
の短縮化を防止し得る他ＮＰＮバイポーラ・トランジス
タのベース抵抗を下げて高速化し得る効果を有する。As explained in detail above, according to the present invention, the reaction between the electrode material and the polysilicon layer can be greatly enhanced without deteriorating the device characteristics of the NPN bipolar transistor or the N-channel MOS field effect transistor having a shallow diffusion layer. Since this can be effectively prevented, shortening of the electrode life, that is, the wiring life can be prevented, and the base resistance of the NPN bipolar transistor can be lowered to increase the speed.
第１図は本発明の一実施例を示す半導体装置の断面図、
第２図は本発明の他の実施例を示す半導体装置の断面図
、第３図は従来のパイ・モス（Ｂｉ−ＭＯＳ）半導体装
置の断面構造図である。
１・・・Ｐ形半導体基板、２・・・Ｎウェル、３・・・
Ｐ＋ソース領域、４・・・Ｐ＋ドレイン領域、５，９・
・・シリコン・ゲート電極、６・・・Ｐウェル、７・・
・ｎ′″ソース領域、８・・・ｎ＋ドレイン領域、１０
．１１・・・Ｎ形コレクタ領域、１２・・・Ｐ形ベース
領域、１３・・・ｎ“エミッタ領域、１４ａ、１５ａ・
・・ソース電極、１４ｂ、１５ｂ・・・ドレインを極、
１６ａ・・・ベース電極、１６ｂ・・・エミッタ電極、
１６ｃ・・・コレクタ電極、１７・・・Ｐ形ポリシリコ
ン層、１８・・・Ｎ形ポリシリコン層、１つ・・・厚膜
フィールド絶縁膜、２０・・・リン硅酸ガラス膜（ＰＳ
Ｇ）、２１・・・高融点金属のシリサイド層、２２・・
・高融点金属のポリサイド層、２３・・・ＣＶＤシリコ
ン酸化膜、２４・・・遷移金属からなるバリア層（Ｔｔ
Ｎ）。FIG. 1 is a cross-sectional view of a semiconductor device showing an embodiment of the present invention;
FIG. 2 is a sectional view of a semiconductor device showing another embodiment of the present invention, and FIG. 3 is a sectional view of a conventional Bi-MOS semiconductor device. 1...P-type semiconductor substrate, 2...N well, 3...
P+ source region, 4... P+ drain region, 5, 9.
...Silicon gate electrode, 6...P well, 7...
・n′″ source region, 8...n+ drain region, 10
．． DESCRIPTION OF SYMBOLS 11... N type collector region, 12... P type base region, 13... n'' emitter region, 14a, 15a.
...source electrode, 14b, 15b...drain as a pole,
16a...Base electrode, 16b...Emitter electrode,
16c...Collector electrode, 17...P type polysilicon layer, 18...N type polysilicon layer, one...thick film field insulating film, 20...phosphosilicate glass film (PS
G), 21... Silicide layer of high melting point metal, 22...
・Polycide layer of high melting point metal, 23...CVD silicon oxide film, 24...barrier layer made of transition metal (Tt
N).
Claims (3)
の接触部分にはそれぞれ高融点金属のポリサイド層およ
びシリサイド層を、またｎ＾＋コレクタ拡散層との接触
部分には高融点金属のポリサイド層またはシリサイド層
をそれぞれ介在せしめる取出電極を備えるＮＰＮバイポ
ーラ・トランジスタを含むことを特徴とする半導体装置
。(1) A polycide layer and a silicide layer of high-melting point metal are applied to the contact areas with the n^+ emitter diffusion layer and the P-type base diffusion layer, respectively, and a high-melting point metal polycide layer and silicide layer are applied to the contact areas with the n^+ collector diffusion layer, respectively. 1. A semiconductor device comprising an NPN bipolar transistor having lead electrodes each having a polycide layer or a silicide layer interposed therebetween.
界効果トランジスタのｎ＾＋ソース、ドレイン拡散層と
の接触部分にはそれぞれ高融点金属のポリサイド層を、
またＰ形ベース拡散層およびＰチャネルＭＯＳ電界トラ
ンジスタのＰ＾＋ソース、トレイン拡散層との接触部分
には高融点金属のシリサイド層を、更にｎ＾＋コレクタ
拡散層との接触部分には高融点金属のポリサイド層また
はシリサイド層をそれぞれ介在せしめる取出電極を備え
るＮＰＮバイポーラ・トランジスタ、ＮチャネルＭＯＳ
電界効果トランジスタおよびＰチャネルＭＯＳ電界効果
トランジスタを含むことを特徴とする特許請求の範囲第
（１）項記載の半導体装置。(2) A polycide layer of a refractory metal is applied to the n^+ emitter diffusion layer and the contact portions with the n^+ source and drain diffusion layers of the N-channel MOS field effect transistor, respectively.
In addition, a silicide layer of a high melting point metal is applied to the contact area with the P type base diffusion layer and the P^+ source and train diffusion layers of the P channel MOS electric field transistor, and a high melting point metal silicide layer is applied to the contact area with the n^+ collector diffusion layer. NPN bipolar transistor, N-channel MOS, equipped with lead electrodes each having a metal polycide layer or silicide layer interposed therein
The semiconductor device according to claim (1), characterized in that it includes a field effect transistor and a P-channel MOS field effect transistor.
層と電極材との間に前記電極材の遷移金属からなるバリ
ア層を付加形成することを特徴とする特許請求の範囲第
（１）項または第（２）項記載の半導体装置。(3) A barrier layer made of a transition metal of the electrode material is additionally formed between the polycide layer or silicide layer of the high melting point metal and the electrode material. The semiconductor device described in (2).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20815486A JPS6362369A (en) | 1986-09-03 | 1986-09-03 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20815486A JPS6362369A (en) | 1986-09-03 | 1986-09-03 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6362369A true JPS6362369A (en) | 1988-03-18 |
Family
ID=16551539
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20815486A Pending JPS6362369A (en) | 1986-09-03 | 1986-09-03 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6362369A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0584858A (en) * | 1991-07-18 | 1993-04-06 | Sanyo Chem Ind Ltd | Skin integrated polyurethane foam molded product and production thereof |
| JPWO2013190759A1 (en) * | 2012-06-21 | 2016-02-08 | パナソニックＩｐマネジメント株式会社 | Solid-state imaging device and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5730366A (en) * | 1980-07-30 | 1982-02-18 | Oki Electric Ind Co Ltd | Schottky transistor and manufacture thereof |
| JPS60201655A (en) * | 1984-03-27 | 1985-10-12 | Seiko Epson Corp | Semiconductor device |
-
1986
- 1986-09-03 JP JP20815486A patent/JPS6362369A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5730366A (en) * | 1980-07-30 | 1982-02-18 | Oki Electric Ind Co Ltd | Schottky transistor and manufacture thereof |
| JPS60201655A (en) * | 1984-03-27 | 1985-10-12 | Seiko Epson Corp | Semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0584858A (en) * | 1991-07-18 | 1993-04-06 | Sanyo Chem Ind Ltd | Skin integrated polyurethane foam molded product and production thereof |
| JPH0759389B2 (en) * | 1991-07-18 | 1995-06-28 | 三洋化成工業株式会社 | Surface-integrated polyurethane foam molded product and its manufacturing method |
| JPWO2013190759A1 (en) * | 2012-06-21 | 2016-02-08 | パナソニックＩｐマネジメント株式会社 | Solid-state imaging device and manufacturing method thereof |
| US9735204B2 (en) | 2012-06-21 | 2017-08-15 | Panasonic Intellectual Property Management Co., Ltd. | Solid-state imaging device and method for manufacturing the same |
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