JPS6360557A - Semiconductor memory cell - Google Patents

Abstract

PURPOSE:To stabilize the operation of an FET while reducing the stepped section of a semiconductor layer by positioning a substrate region in the FET onto a thin insulating film on a semiconductor substrate or a diffusion layer formed into the substrate and supplying the semiconductor substrate or the diffusion layer under the thin insulating film with fixed voltage. CONSTITUTION:A substrate region 15 in an FET for switching functions as a back gate through a thin insulating film 17 by a P-type region 13 connected to a cell plate 16. when a semiconductor layer is grown for shaping the FET, the thin insulting film 17 is only formed as a stepped section. Accordingly. the FET for switching is not operated unstably because the region 13 giving a back bias is arranged just under the FET through the thin insulating film 17, and the excellent semiconductor layer can be shaped easily because the stepped section of the semiconductor layer forming the FET can be reduced.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to a semiconductor memory cell suitable for high integration.

(Prior art and its problems) A cell plate placed on the inner wall of a groove formed on the surface of a semiconductor substrate along the outer periphery with an insulating film interposed therebetween, a charge storage region placed inside the semiconductor substrate, and a cell plate on the semiconductor substrate. MO formed on a semiconductor layer grown on top with an insulating film interposed
The 1-transistor 1-Vacita type memory cell composed of SFET was presented at the International Electronic Devices Conference held in 1985:
Abstract of i (IEDII)? , 718-7
It has been proposed as "r SSS cell" by Ohkura et al. 21.

3(a) is a sectional view of the SSS cell in the bit line direction, and FIG. 3(b) is a sectional view taken along line AA' in FIG. 3(a) in the word line direction.

The cell plate of the SSS cell is composed of a conductor N16 placed on the inner wall of a groove formed on the surface of a P-type semiconductor substrate 11 with an insulating film 17 interposed therebetween. Supplied. The charge storage region is composed of an N-type region 12 formed on the surface of a P-type semiconductor substrate 11, and is in contact with an insulating film 17 on the inner wall of the trench. A MOS for switching is formed by an N-type region 18 forming a first current-carrying electrode, an N-type region 19 forming a second current-carrying electrode, a P-type region 15 forming a substrate region, and a conductor layer 20 forming a word line.
A FET is configured, a first current-carrying electrode is connected to a conductor layer 22 constituting a bit line, and a second current-carrying electrode is connected to a charge storage region. This switching MOSFET is formed in a semiconductor layer that is allowed to grow on a cell plate on a semiconductor substrate with an insulating film interposed therebetween.

The main features of the SSS cell are that a large cell capacity can be obtained with a shallow trench depth, no interference occurs between cells, and no element isolation region is required.

Generally, if the substrate area of a MOSFET is electrically floating, the operation of the MOSFET tends to become unstable, so
In an SS cell, a cell plate to which a constant voltage is supplied is placed directly below the cell plate in an attempt to help prevent unstable MOSFET operation. However, in SSS cells, the insulating film between the cell plate and the semiconductor layer forming the MOSFET must be a film grown by oxidizing the conductor layer that makes up the cell plate, or a film grown by CVD. . The film quality of these insulating films is not very good, so the film quality has to be made thicker, which is not good for the operational stability of the MOSFET mentioned above.

Furthermore, when crystallizing a semiconductor layer for forming a MOSFET, the contact surface between the second current-carrying electrode and the substrate region is used as a seed, but since the step of the cell plate is large, various complicated techniques must be used.

Therefore, an object of the present invention is to eliminate such conventional drawbacks, to obtain a large cell capacity with a shallow groove depth, to prevent interference between cells, to eliminate the need for an element isolation region, and to achieve an FE
Because the insulating film directly under the semiconductor layer forming T can be made thinner
It is an object of the present invention to provide a semiconductor memory cell in which the operation of an ET does not become unstable, and in addition, a high-quality semiconductor can be easily formed because the step difference in the semiconductor layer forming the FET can be made small.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the semiconductor memory cell provided by the present invention is arranged on the inner wall of a groove formed on the surface of a semiconductor substrate along the outer surface with an insulating film interposed therebetween. This FE"f
The substrate region is located on a thin insulating film on a semiconductor substrate or a diffusion layer formed in the semiconductor substrate, and a constant voltage is supplied to the semiconductor substrate or the diffusion layer under the thin insulating film. do.

(Example) Examples of the present invention will be described in detail below with reference to the drawings.

FIG. 1(a) is a cross-sectional view of an embodiment of the present invention in the direction of lines B, T, and FIG. be. Note that FIG. 1 shows an embodiment corresponding to a folded-rad bit line configuration.

11 is a P type substrate. N-type region 12 constitutes a charge storage region. The P-type region 13 is electrically connected to the cell plate and constitutes a back gate portion of the switching FET. The N-type region 14 constitutes a connection portion that electrically connects the second current-carrying pole of FEI' and the charge storage region. P
The mold region 15 constitutes the substrate region of FE'I. The conductor layer 16 is completely disposed within the groove with an insulating film 17 interposed therebetween, constitutes a cell plate, and is supplied with a constant voltage. The N-type region 18 constitutes the first current-carrying 'wL pole of the FET. N-type region 19 constitutes the second current-carrying electrode of the FET, and N-type region 1
4 to the charge storage region. Here, the P type region 15, N type region 18, and N type region 19 are formed in a semiconductor substrate or a semiconductor layer grown on an insulating film. The conductor layer 20 constitutes one gate pole of the FET and also serves as word line wiring. The conductor layer 21 is a word line wiring for accessing adjacent cells. The conductor layer 22 constitutes a bit line,
The first terminal of the FET is connected to the rlL electrode. 23.24
is an insulating film.

The substrate region of the switching FET is back gated through a thin insulating film 17 by a P-type region 13 connected to the cell plate. In addition, when growing a semiconductor layer for forming an FET, a step is created by forming a thin insulating film 1.
There are only 7.

FIG. 2(a) is a cross-sectional view in the pit line direction of another embodiment of the present invention whose structure is different from FIGS. 1(a) and (b), and FIG. It is a sectional view taken in the word line direction at -A'. Incidentally, FIG. 2 shows an embodiment corresponding to a folded-Rad-pit line configuration.

11 is a P type substrate. N-type region 12 constitutes a charge storage region. P-type region 15 constitutes the substrate region of the FET. The conductor layer 16 is placed in the groove via an insulator WX17, constitutes a cell plate, and is supplied with a constant voltage. N-type region 18 constitutes the first current-carrying electrode of FE'I'. The N-type region 19 constitutes a second carrying electrode of FE'ff and is fully connected to the charge storage region. Here, P type region 15
, N-type region 18, and N-type region 19 are formed in a semiconductor layer grown on a semiconductor substrate or an insulating film. The conductor layer 20 constitutes the gate electrode of FE'I' and also serves as word line wiring. The conductor layer 21 is a word line wiring for accessing adjacent cells. The conductor layer 22 constitutes a pit line, and the FE
It is connected to the first current-carrying electrode of T. 23 and 24 are insulating films.

The substrate region of the switching FEr is back gated by the P-type substrate 11 with a thin insulating film 17 interposed therebetween. Further, when growing the semiconductor layer for forming the FET, the only difference in level is the thin insulating film 17.

For convenience of explanation, an example in which an N-type channel MO5FET is used as the FET has been described above, but the present invention is applicable to other FEs.
It can also be applied when T is used. In addition, FEr can be formed not only in epitaxially grown semiconductor layers, but also in various semiconductor layers, such as polycrystalline semiconductor layers, those processed by appropriate methods, and those that can be made into single crystals by further appropriate methods. Can be done.

(Effects of the Invention) In the semiconductor memory cell of the present invention, a large cell capacity can be obtained with a shallow trench depth, no interference occurs between cells, and no element isolation region is required. Moreover, since the switching FET has a region that applies back bias directly below it through a thin insulating film, its operation does not become unstable, and the FET
In order to reduce the step difference in the semiconductor layer forming the ET,
A high quality semiconductor layer can be easily formed. As described above, the effects of the present invention are very large.

[Brief explanation of the drawing]

FIG. 1(a) is a sectional view in the bit line direction of an embodiment of the present invention, FIG. 1(b) is a sectional view in the word line direction taken along line AA' in FIG. FIG. 2(a) is a cross-sectional view in the bit line direction of another embodiment of the present invention whose structure is different from that in FIG. 1, and FIG. 2(b) is a cross-sectional view taken along line AA' in FIG. A cross-sectional view in the word line direction, FIG. 3(a) is S
A cross-sectional view of the SS cell in the bit line direction, FIG. 3(b) is the third
FIG. 2 is a cross-sectional view taken along line AA' in the figure (,) in the word line direction. 12: N-type 1 territory 18: N-ge yearning area 23, 24+
Fujuen 15: P type stubbornness
b) He m< tflll^ 8

Claims (2)

[Claims] (1) A cell plate disposed on the inner wall of a groove formed on the surface of the semiconductor substrate along the outer periphery with an insulating film interposed therebetween; a charge storage region disposed within the semiconductor substrate so as to be in contact with the insulating film; or an FET formed on a semiconductor layer grown on an insulating film, the substrate region of this FET is located on a thin insulating film on a semiconductor substrate or a diffusion layer formed in a semiconductor substrate, and the thin insulating film A semiconductor memory cell characterized in that a constant voltage is supplied to a semiconductor substrate or a diffusion layer underneath. (2) The semiconductor memory cell according to claim 1, wherein the thin insulating film has a thickness of 50 nanometers or less.