JPS60176267A - Semiconductor memory device and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce the area of a capacitance section, and to improve the degree of integration by forming a pair of second conduction type regions to a pair of opposite side walls in a groove shaped to the surface of a first conduction type semiconductor substrate and shaping a second conduction type region as a source electrode in an MIS Tr electrically connected and shaped to the regions. CONSTITUTION:An SiO2 film 12, a silicon nitride film 13, an SiO2 film 14 and a resist 15 are formed on a P type Si single crystal substrate 11 in succession, and a groove A is shaped through selective etching. A diffusion layer 20 consisting of P is shaped on the groove, a deep groove B is further formed, and SiO2 21 is formed on the surfaces of the grooves and an impurity layer 22 on the bottom of the groove. The SiO2 film 14, the silicon nitride film 13, the SiO2 film 12, a resist 23 and the silicon dioxide film 21 are removed, an SiO2 film 24, an silicon nitride film 25 and polycrystalline Si 26 to which P is doped are shaped in the grooves in succession, and an SiO2 film 27 and an SiO2 film 27' are formed on the surface. SiO2 27' on an element region is removed, a thin SiO2 film 28 is shaped, gate electrodes 29, 29' are formed, and diffusion layers 30A, 30A', 30B, 30B' are formed simultaneously through an ion implantation method.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of a charge storage section in a semiconductor memory device including a capacitor serving as a charge storage section and an insulated gate field effect transistor, and a method for manufacturing the same.

Semiconductor memory cells that store binary information in the form of charges have a small cell area, making them highly integrated, large-capacity, and excellent as memory cells. In particular, a memory cell consisting of one transistor and one capacitor (hereinafter abbreviated as 1TIC cell) is important as a memory cell for highly integrated memory because it has few components and has a small cell area. With the reduction in memory cell size due to higher integration of memory, the area of the capacitor in the ITIC cell structure is decreasing.The decrease in the amount of stored charge due to the decrease in the area of the capacitor is due to the problem of resistance to alpha particles and the sensitivity of the sense amplifier. cause deterioration.

Conventionally, in order to solve these problems, a method of forming a large storage capacitor despite the reduction in memory cell area was to create a groove in the semiconductor substrate and form a capacitor between the side surface of the groove and the semiconductor substrate. It tells you how to do it.

FIG. 1 shows an example of a conventionally well-known ITIC cell in which a capacitive portion is formed using a trench. In Figure 1, 3
is a capacitor electrode, and a thin insulating film 2 is provided between it and the inversion layer 6 to form a storage capacitor section. Reference numeral 4 denotes a gate electrode of a switching transistor, which is connected to a word line and controls the movement of charges between a diffusion layer 5 and an inversion layer 6, which are connected to a bit line.

However, in the conventional l
Due to its structure, the TIC cell has a trench formed in the element region as a capacitive portion. Therefore, the cell size inevitably increases by the size of the groove forming region and the margin between the groove and the isolation region. In the future, as higher integration progresses and miniaturization of cell dimensions is required, conventional ITIC cells using grooves have the disadvantage that there will be a limit to miniaturization of cell size due to their structure.

SUMMARY OF THE INVENTION An object of the present invention is to provide a capacitor structure suitable for high integration by extremely reducing the area of the capacitor in an ITIC cell in which the capacitor is formed using a trench, and a method for manufacturing the same.

According to the present invention, a pair of second conductivity type regions formed on a pair of opposing sidewalls of a groove provided in a surface of a first conductivity type semiconductor substrate, an insulating material covering at least the inner wall of the groove portion, and the insulating material A conductive material is provided on the surface of the first conductive type semiconductor substrate, and is in contact with the insulating material and is electrically connected to the second conductive type region. A semiconductor memory device characterized in that it includes a second conductivity type region which is a source electrode of an MI8 transistor is obtained.

Furthermore, according to the present invention, the first conductive type semiconductor substrate is
a step of forming a first second conductivity type region on an inner wall of the first trench in the capacitor formation region;
a step of forming a second groove by etching the bottom of the groove; a step of forming a first conductivity type region at the bottom of the second groove; a step of forming an insulating film on the surface of the second groove;
a step of filling the inside of the second groove with a conductive material; a step of covering the upper part of the conductive material with an insulating material; A method for manufacturing a semiconductor memory device is obtained, which includes a step of forming a second conductivity type region.

Hereinafter, typical embodiments of the present invention will be described in detail using the drawings.

Fig. 2 fal, (bl, (c), td)
, tel, if), (g), th).

(il, (j) are schematic cross-sectional views sequentially showing the manufacturing process of forming a capacitive part using grooves in the present invention.

FIG. 2 (al) shows that after sequentially forming a thin silicon dioxide film 12, a silicon nitride film 13, and a thick silicon dioxide film 14 on a p-type silicon single crystal substrate 11, areas other than the groove forming region are covered with a resist 15; Furthermore, using this resist 15 as an etching mask, the silicon dioxide film 15, silicon nitride film 14, and silicon dioxide film 13 are sequentially etched and removed by reactive sputter etching, and then the silicon dioxide film 15 and silicon dioxide film 14 are used as an etching mask to remove the silicon dioxide film 15, silicon nitride film 14, and silicon dioxide film 13 in sequence. A state in which the first groove A is formed by etching the substrate 11 is shown.

FIG. 2(b) shows that after removing the resist 15, a silicon dioxide film 16 is formed on the surface of the groove A by thermal oxidation.
Thereafter, a resist 17 is applied to the entire surface, and a thin layer of silicon 18 is further deposited on the surface, and a resist 19 is shown covering the area other than the area that will become the groove capacitance.

FIG. 2 (C1 shows that the silicon I8 is etched using the resist 19 as an etching mask, and then the resist 1 is etched using the silicon 18' as an etching mask.
7 is shown after being etched away. Here resist 1
One means of etching 7 is, for example, a reactive sputter etch technique using oxygen gas.

FIG. 2 (cl+) shows that after the silicon 18' is removed, the silicon dioxide film 16 is etched away using the resist 17' as an etching mask, and then the silicon dioxide film 14 is used as a mask to remove only the inside of the trench in the capacitor formation region. A diffusion layer 20 of an impurity of a conductivity type different from that of the silicon substrate 11, for example, phosphorus.
This shows the state in which it has been formed.

At t6+ in FIG. 2, the silicon substrate 11 is etched by reactive sprocket etching using the silicon dioxide film 14 as an etching mask to form a deeper trench B, and then a silicon dioxide film 21 is formed on the surface of the trench by thermal oxidation. form,
Next, using the silicon dioxide film 14 as a mask, an impurity layer 22 of the same conductivity type as the substrate 11 is formed at the bottom of the groove B by ion implantation.
This shows the state in which it has been formed.

FIG. 2(f) shows a state in which after the resist is formed on the entire surface, the resist 23 is left only in the grooves by reactive S/NO etch using oxygen gas in the same manner as described above.

FIG. 2(g) shows the silicon dioxide film 14, silicon nitride film 13 and silicon dioxide film 12 using the resist n as a mask.
This shows the state in which the parts have been removed by sequential etching.

FIG. 2(h) shows a state in which, after removing the resist 23 and the silicon dioxide film 21, a silicon dioxide film 24, a silicon nitride film 25, and a phosphorous-doped polycrystalline silicon 26 are successively formed over the entire surface of the wafer. Here, the phosphorus-doped polycrystalline silicon 26 is formed thickly so as to sufficiently fill the groove.

FIG. 2(i) shows that the phosphorus-doped polycrystalline silicon 26 is etched from the surface to leave the phosphorus-doped polycrystalline silicon 26' only in the groove, and then the silicon nitride film 25 is masked and filled in the groove. Phosphorus-doped polycrystalline silicon 26'
This shows a state in which a silicon dioxide film 27 is formed on the top of the trench by oxidizing the silicon dioxide film. Since the silicon nitride film 25 is formed thinly, when the phosphorus-doped polycrystalline silicon is oxidized, the silicon nitride film 25 is formed thinly.
5 is completely oxidized, but there is a large difference in oxidation rate between the phosphorus-doped polycrystalline silicon 26' and the silicon nitride film 25, and the thickness of the silicon dioxide film 27' on the element region and the silicon dioxide film on the isolation region are different. There is a big difference between the thickness.

FIG. 2(j) shows that after removing the silicon dioxide film 27' on the element area, a thin silicon dioxide film path is formed on the element area by thermal oxidation, and then the switching transistor connected to the word line is formed. Forming the gate electrodes 29, 29', and then forming a diffusion layer 30A connected to the bit line,
30A' and diffusion layers 3QB and 30B' electrically connected to the diffusion layer 20' are simultaneously formed by ion implantation.

FIG. 2fj) shows a schematic cross-sectional view of a semiconductor memory device formed according to the present invention. Using this, the operation of the semiconductor memory device according to the present invention will be described below. When storing charges, by turning on the switching transistor connected to the word line, the diffusion layer 20 formed on the side wall of the trench is moved from the diffusion layer 30A tangent to the bit line.
Charge is accumulated in ' and becomes a memory state. However, the phosphorus-doped polycrystalline silicon 26' buried in the trench is grounded.

At this time, the storage cap consists of the capacitance of the insulating film formed between the phosphorus-doped polycrystalline silicon 26', which is a capacitance electrode, and the diffusion layer 20', and the depletion layer capacitance spread from the diffusion layer 20' into the silicon substrate 11. Consists of the sum of When reading out the stored charges, the switching transistor connected to the word line is turned on, and the charges accumulated in the diffusion layer 20' are transferred to the diffusion layer 30A connected to the bit line.

As described above, the operation of the semiconductor memory device according to the present invention is the same as that of the conventional one. As in the conventional case, the storage capacity can also be easily increased by increasing the depth of the grooves formed. However, the semiconductor memory device according to the present invention differs greatly from the conventional one in that the trench is formed in the isolation region, that is, the isolation region also serves as a capacitor. By forming a trench in the isolation region, the size of the semiconductor memory device can be significantly reduced compared to a conventional semiconductor memory device in which a trench is formed in the element region. Since the phosphorus-doped polycrystalline silicon buried in the groove is grounded, sufficient isolation characteristics between the clusters can be obtained. Furthermore, I love you! Since the phosphorus-doped polycrystalline silicon that serves as the pole is buried in the groove, the element surface is flat.

As described above, according to the present invention, a large storage capacity can be obtained even in a small area, so that a semiconductor memory device suitable for high integration can be easily obtained.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view of an ITIC cell in which a capacitor portion is formed using a conventional groove, and FIG. (b), (C), (d), te), (
f) , (gl, lhl * (i) t (j
) is a schematic cross-sectional view showing an example of the present invention following the process. In the figure, each symbol indicates the following. 1.11: Silicon substrate, 2 , 12 , 14 , 16
, 21 , 24 . 27.27', 28: silicon dioxide film, 3, 26':
Capacitor electrode, 4, 29, 29': Gate electrode of switching transistor connected to word line, 5.3O
A, 30A': Diffusion layer connected to bit line, 6: Inversion layer, 13.25: Silicon nitride film, 15, 17.17'
, 19, 23 Niresist, 18, 18': Silicon, 20, 20', 30B, 30B':
Impurity diffusion layer of a conductivity type different from that of the substrate, 22: Impurity diffusion layer of the same conductivity type as the substrate, A, B: Groove. 71-1 Figure 72 Figure (a) (b) (C) O 2 Figure (d) (e) 9th (fn) 72 Figure ((]) (1-1) (i) 72 Figure (j)

Claims (2)

[Claims] (1) A pair of second conductivity type regions formed on a pair of opposing sidewalls of a groove provided on the surface of a first conductivity type semiconductor substrate, an insulating material covering at least the inner wall of the groove, and a region in contact with the insulating material; a conductive material applied with a reference potential to fill the groove, an M-type formed on the surface of the first conductivity type semiconductor substrate, in contact with the insulating material, and electrically connected to the second conductivity type region; A semiconductor memory device comprising a second conductivity type region which is a source electrode of an S transistor. (2) forming a first groove on a first conductivity type semiconductor substrate;
a step of forming a conductivity type region; a step of etching the first groove bottom to form a second groove; a step of forming a first conductivity type region in the second groove bottom; a step of forming an insulating film on the surface of the second groove; a step of filling the inside of the second groove with a conductive material; a step of covering the upper part of the conductive material with an insulating material; 1. A method of manufacturing a semiconductor memory device, comprising the step of forming a conductivity type region.