JPS6359664A - Information processor - Google Patents

Abstract

PURPOSE:To immediately start a following instruction when read start elements are not superposed so as to reduce a useless waiting by providing a means which detects that the region on a vector register for a leading instruction and the read start element on the vector register for the following instruction are not superposed. CONSTITUTION:A comparator 16 compares the sizes of a storage start number n1 with operated data read start number n2 and an overflow detection circuit 15 detects whether n1+vL (vector length) exceeds a maximum vector length (MaxVL). When the output from the comparator 16 is n2<n1, and the output from the overflow detection circuit 15 is n1+vL>MaxVL, if the output from an adder 14 is the residual of a divisional formula such as dividing n1+vL by MaxVL, that is, [n1+VL]modMaxVL<n2, a following instruction starting signal is transmitted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and more particularly, to control of village calculations in an information processing device equipped with a plurality of vector registers that can be written to and read from at any timing. Related to operation activation control of commands that specify elements.

[Conventional technology]

Conventionally, in an information processing device equipped with a plurality of vector registers that can be read and written at any timing,
When calculating the vector length sequentially from the start element specified by the instruction and calculating the number of elements specified by the nostar, if the storage register of the calculation result by the preceding instruction is input to the calculation light register of the subsequent instruction, the calculation result by the subsequent instruction When the operation start element of the operation is the 0th element (0 origin, meaning the first element).

As shown in FIG. 4(a), the operation result of the first element in the preceding operation instruction is written to the 4-bit register, and at the same time this operation result is read out and activated for the subsequent instruction so that it can be used in the subsequent instruction. put on.

On the other hand, if the calculation start element is not the O-th element, then
), the subsequent instruction is activated when the writing of the vector register by the preceding operation instruction is completed, that is, when the preceding operation instruction is completed. In this case, it is guaranteed that all operations are executed after the operation result of the preceding instruction is stored in the arithmetic unit element of the subsequent instruction. In this way, since the operation start element is an undefined value (varies depending on the instruction) specified by the instruction, if the start element is other than the 0th element, it is necessary to wait for the completion of the preceding instruction.

[Problem that the invention seeks to solve]

In this way, in the conventional information processing apparatus described above.

If the operation start element is other than the 0th element, in order to fully guarantee the order of instruction execution, control is performed so that the operation is started after waiting for the preceding instruction that stores the operation result in the operation unit register to be completely completed. are doing.

However, when controlling as described above, if the rewriting of register contents by the preceding instruction does not affect the operation of the succeeding instruction, even if it is unrelated to the order of the preceding instruction, the completion of the preceding instruction is waited for. Therefore, there is a problem that this becomes a factor that hinders the improvement of vector processing performance.

[Means for solving problems]

The present invention includes a plurality of vector registers, and a vector arithmetic unit that receives data from the vector registers, performs a predetermined operation, and deposits the results of the operation into the vector register specified by all instructions.

In an information processing device that allows an operation to be started from any vector element of a vector register specified by an instruction, there is a vector register in which the results of the operation by the preceding instruction are written, and a vector register from which data is read during the operation by the subsequent instruction. If the vector registers are the same, there is a gravitational force between the area on the vector register where the operation result by the above preceding instruction is written and the read start element on the vector register from which data is read during the operation by the above subsequent instruction. The present invention is characterized in that it includes a detecting means for detecting, and if the detecting means does not detect an overlap between the above-mentioned area and the read start element, the operation according to the above-mentioned subsequent instruction is immediately started.

〔Example〕

The present invention will be explained below with reference to Examples.

FIG. 1 is a block diagram showing an embodiment of an information processing apparatus according to the present invention, and FIG. 2 is a block diagram showing an embodiment of a control section used in the present invention.

First, referring to FIG. 1, an information processing apparatus according to the present invention includes a plurality of vector registers 1a to In, a plurality of arithmetic units 2a
~2n+ and a control section 3.

Vector registers 18-1n are connected to arithmetic units 2a-2n via data transfer path 4. The above control unit 3
sends out a subsequent instruction activation enable signal, which will be described later.

The configuration of the control section will be explained with reference to FIG. 1
1 is an instruction register that holds all instructions to be determined whether or not an operation is started; 12 is a vector length register (VL) that holds the vector length data of the instruction held in instruction register 1; A register that stores the starting element number for storing the operation results of the vector instruction that is being multiplied and executed.

14 is an adder that calculates an interest rate modulo the maximum vector length between the calculation result storage start element number n1 of the vector instruction being executed stored in register 3 and the vector length vL of the vector instruction; 15 is an adder 14 overflow detection circuits, and this overflow detection circuit 15 is the above-mentioned n
It is used as a means to detect that 1+vL exceeds the maximum vector length (Max VL) f. 16 and 17 are comparison circuits, respectively (calculation data read start number n2 of the instruction about to be activated) > (computational result storage start element number J of the instruction being executed) and nl +vL
<nz ffi detected. 18 is a combinational circuit, which includes an overflow detection circuit 15. It receives the signals from the comparison circuits 16 and 17, detects the activation enable condition for the subsequent instruction, and outputs the subsequent instruction activation enable signal.

Here, a case will be described in which a vector instruction with an operation result storage start element n11 and a vector length vL is executed first, and then a calculation data read start element number n2 is executed.

First, calculation result storage start element number n1 + vector length v
The L vector instructions are stored in the instruction holding register 11, the operation is activated, and the operation is started. and 1
At the next timing, the above calculation result storage start element number n,
is transferred to and stored in the register 13. At the same time, the vector instruction with the calculation data read start element number n2 is stored in the instruction holding register 1. Then, the vector instruction with the calculation data read start element number n2 (subsequent vector instruction)
Check whether it is possible to start the calculation.

The comparison circuit 16 compares the storage start number n1 and the calculated data readout start number n2, and the overflow detection circuit 15 compares whether nl-1-vL (vector length) exceeds the maximum vector length (Max ML) k. Detect. Further, the comparison circuit 17 compares n1+vL (vector length) with the calculated data read start number n2. The detection result of the overflow detection circuit 15 and the comparison result of the comparison circuits 16 and 17 described above are input to the combinational circuit 18.

In the combinational circuit 18, FIGS. 3(a), (b) and (
Check whether the conditions shown in e) are satisfied. In other words,
As shown in FIG. 3(a), the output of the comparison circuit 16 is n2>
+g.

If the output of the comparison circuit 17 is 11 +vL<12, it is assumed that the area where the operation result by the preceding instruction is written does not overlap with the read start element from which the data for the operation by the subsequent instruction is read, and the combinational circuit 18 issues a subsequent instruction activation enable signal. Send out. Similarly.

As shown in FIG. 3(b), the output of the comparison circuit 16 is n2<
nl, the output of the overflow detection circuit 15 is nl-1
If -vL≦MaxVL, the nine combinational circuit 18 sends out all command activation enable signals, which will be described later.

On the other hand, as shown in FIG. 3(C), the output of the comparison circuit 16 is n2<nl, and the output of the overflow detection circuit 15 is n
1 + vL ) Max VL, the output from the overflow detection circuit 15 is nl as described above.
Since +vL>MaxVL, the output of the adder 14 is n
The remainder I) divided by 1+vLf Max VL is output. That is.

Cn 1 + VL]. . dMaxVL is output. Therefore, if the output of the comparison circuit 17 is ["1+v") mod MaxVL<n2, the two-combination circuit 18 sends out all subsequent instruction enable signals.

This subsequent instruction activation enable signal causes the instruction activation to be applied to the instruction with the calculation data read start element number n2.

〔Effect of the invention〕

As explained above, in the second aspect of the present invention, a vector register in which a preceding instruction stores all operation results is used as a data read register by a subsequent instruction.

A means is provided for detecting that the area on the vector register where the preceding instruction writes the operation result and the read start element on the vector register where the subsequent instruction reads the data sound for the operation do not overlap, and the above area and the read start element overlap. In cases where it doesn't.

This allows subsequent instructions to be activated immediately.

Reduced unnecessary waiting when starting 4 vector commands.

This has the effect of achieving efficient covering torque performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing main parts of an information processing apparatus according to the present invention, FIG. 2 is a block diagram showing an embodiment of the control section shown in FIG. 1, and FIGS. 3(a), (b) and ( C) is a case in which the control unit sends a subsequent command activation enable signal.'
Figure 4 (a) and (b) are diagrams for explaining the activation of conventional preceding and succeeding instructions. 1a, 1b,..., In... Vector register. 2 a +..., 2n... Arithmetic unit, 3... Control unit, 11... Instruction holding register, 12... Vector length holding register. 13...Arithmetic result storage start element number holding register. 14... Adder, 15... Overflow detection circuit. 16.17...Comparator, 18...Combination circuit. Look-ahead order + activation possible sequence 3 diagrams

Claims (1)

[Claims] 1. It has a plurality of vector registers and a vector arithmetic unit that receives data from the vector registers, performs predetermined operations, and sequentially writes the results of the operations to the vector registers specified by the instruction. In an information processing device in which an operation can be started from any vector element of a vector register, the vector register to which the operation result by the preceding instruction is written is the same as the vector register from which data is read during the operation by the subsequent instruction. In the case of the present invention, there is provided a detecting means for detecting that an area on the vector register into which the operation result by the preceding instruction is written does not overlap with a read start element on the vector register from which data is read during the operation by the subsequent instruction, An information processing apparatus characterized in that, if the detecting means does not detect an overlap between the area and the read start element, an operation by the subsequent instruction is immediately started.