JP2693930B2 - Vector processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION This patent relates to vector processing devices, and more particularly to transporting vector element data between storage means.

[0002]

2. Description of the Related Art FIG. 3 shows an example of a conventional vector processing device of this type, which is an instruction control unit 301 for controlling an instruction.
And a plurality of vector registers 311, 312, 313 holding the vector element data, a crossbar 314 for transferring the vector element data in the vector pipeline operation unit, and a plurality of operation units 315, 316. And a vector pipeline operation unit 320 having a configuration similar to that of the vector pipeline operation unit 310 and including vector registers 321, 322, 323, a crossbar 324, and operation units 325, 326, and a vector pipeline operation units 310, 3
And a crossbar unit 305 for transferring vector element data between 20 units. The vector element data is the vector registers 311, 312, 313, 321 and 32 in the vector pipeline arithmetic units 310 and 320.
2 and 323 are interleaved and assigned, and the vector pipeline arithmetic units 310 and 320 operate in parallel at the same time.

When performing a partial vector operation on the element data stored in the vector registers 311 and 321, a part of the element data stored in the vector registers 311 and 321 is transferred to another vector register. I need to put it.

For example, in FIG. 2, when a maximum of 32 elements can be handled as a vector unit, and two vector pipeline arithmetic units and two vector registers are used, data is interleaved to allocate data to the vector register 21.
The contents of each vector register when 16 element data indicating 16 to 31 out of 32 element data indicated by 0 to 31 of 1 and 221, are transferred to the vector registers 212 and 222 are shown.

The transfer destination register is the vector register 31.
When carrying out the transfer shown in FIG.
First, the instruction specifies the vector length designation as "16".
Next, the vector register transfer instruction specifies the numbers of the transfer source vector registers 311, 321 and the transfer destination vector registers 312, 322.
1, the vector pipeline operation units 310 and 320 are notified of the instruction start information from the read start address and write start address of the vector register.
Control information is also notified to 05.

In the example of FIG. 2, the vector register 21
When the 16 element data 16 to 31 out of the 32 element data 1 to 221 (number 0) indicated by 0 to 31 are transferred to the vector registers 212 and 222 (number 1), a transfer source is issued by an instruction. The vector register number 0 is specified, the transfer destination vector register number is specified as 1, and the instruction control unit 301 sets the vector register 2 with the number 0.
The read start address of 11 and 221 and the transfer start address specified by the instruction and the number of vector pipeline operation units 3
Calculated from 10, 320, vector registers 311 and 32
The value "8" of the read address of 1 is calculated and notified to the vector pipeline arithmetic units 310 and 320. Further, in this case, the value of the write start address of the vector registers 312 and 322 is notified as "0".

The vector registers 311 and 321 store the element data at the locations indicated by the respective read address registers (not shown) in the respective pipeline arithmetic units 3.
Element data is passed to the crossbar 305 between the vector pipeline arithmetic units 310 and 320 via the crossbars 314 and 324 in the 10, 320. The crossbar 305 receives the data in the internal register, and passes the element data to the pipeline operation units 310 and 320 of the transfer destination instructed by the instruction control unit 301. Pipeline operation unit 310,
320 transmits the element data to the crossbars 314, 3
Write via 24 to the location of the vector register indicated by the write data register (not shown). These operations are continuously repeated (vector length / number of vector pipeline operation units) times while incrementing the read and write addresses of the vector register by one, and the vector register transfer instruction is executed.

[0008]

In the above-described conventional vector processing apparatus, when the vector register transfer instruction is executed, even if the element data is transferred to the vector register in the own vector pipeline operation unit, the pipeline operation unit. Since the transfer is performed via the register in the crossbar that transfers the data between them, it takes extra time for the processing. In that case, the instruction controller issues the next instruction after detecting the end of the vector register transfer instruction.

[0009]

The apparatus of the present invention transfers a plurality of vector registers and a plurality of vector pipeline operation units having a transfer function between the vector registers, and vector element data transfer between the vector pipeline operation units. In a vector processing device having a crossbar for performing the vector data, the element data is operated by another vector pipeline operation according to the value of the transfer start address of the vector register transfer instruction for the element data allocated in order to the plurality of vector pipeline operation units. Section is provided with a transfer instruction determining means for determining whether it is transferred as element data of another vector register of the vector section or as the element data of another vector register of the own vector pipeline operation section, and in the case of the former, From the vector pipeline operation unit Controls to transfer data between vector registers via the crossbar by transferring data between vector pipeline operation units, and in the case of the latter, the vector transfer is performed by the data transfer function in the vector pipeline operation unit. It is characterized by controlling to transfer data between them.

[0010]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

FIG. 1 shows an embodiment of the vector processing device of the present invention, which comprises an instruction control unit 101, a plurality of vector pipeline arithmetic units 110 and 120, and a crossbar 105.

The instruction control unit 101 receives the information of the vector register transfer instruction from the instruction execution control unit 102 that controls the execution of the instruction and the instruction execution control unit 102, and this transfer instruction orders the transfer in the vector pipeline operation unit. A transfer instruction determination circuit 103 for determining whether the transfer instruction is between the vector pipeline operation units,
The information of the vector register transfer instruction from the instruction execution control unit 102 and the determination result from the transfer instruction determination circuit 103 are received,
The transfer instruction timing detecting means 104 detects the timing at which the vector element of the transfer destination address 0 is stored in the vector register.

The vector pipeline operation unit 110 is a vector register 1 for holding vector element data.
11, 112, 113, a crossbar 114 for transferring vector element data in the vector pipeline arithmetic unit 110, and arithmetic units 115, 116.
Similarly, the vector pipeline operation unit 120 also has vector registers 121, 122, 123 and a crossbar 124.
And arithmetic units 125 and 126. Crossbar 1
Reference numeral 05 transfers vector element data between the vector pipeline operation unit 110 and the vector pipeline operation unit 120.

The vector element data is interleaved and assigned to the vector registers 111, 112, 113, 121, 122, 123 in the vector pipeline arithmetic units 110, 120, respectively, and the vector pipeline arithmetic units 110, 120 are simultaneously operated. Operate in parallel.

When performing a partial vector operation on the element data stored in the vector registers 111 and 121, a part of the element data held in the vector registers 111 and 121 is transferred to another vector register. I need to put it. Here, the operation of this embodiment will be described assuming that the transfer shown in FIG. 2 is performed.

The calculation results output from the arithmetic units 115, 116, 125 and 126, or the load data output from the main memory (not shown) are held in the vector registers 111 and 121 as transfer source data. To do.
When the transfer destination register for transferring a part of the element data stored in the vector registers 111 and 121 (number 0) is the vector registers 112 and 122 (number 1), first the vector length designation is set to "16" by an instruction. specify. Next, the vector register transfer instruction specifies the number 0 of the transfer source vector registers 111 and 121 and the number 1 of the transfer destination vector registers 112 and 122. At this time, the transfer instruction determination means 103 receives the information of this transfer instruction, and when the value of (transfer start address) mod (the number of vector pipeline operation units) is 0, it is a transfer instruction in the vector pipeline operation unit. It is determined that the control information is the vector pipeline operation unit 11
0, 120, crossbar 105, and instruction execution control unit 102. Further, the instruction control unit 101 transmits the read start address and write start address of the vector register and the control information of the crossbars 114 and 124 in the vector pipeline operation units 110 and 120 to the vector pipeline operation units 110 and 120.

In the example of FIG. 2, the vector register 21
When the 16 element data 16 to 31 out of the 32 element data 1 to 221, which are indicated by 0 to 31, are transferred to the vector registers 212 and 222, the transfer source vector register number is 0 and the transfer destination is The vector register number is designated as 1, respectively. Since the transfer instruction determination means 103 has the read start address “16” of the vector registers 111 and 121 and the number of vector pipeline operation units “2”, the (transfer start address) mod (the number of vector pipeline operation units) becomes “0”, and It is determined that the vector register transfer instruction can be executed as a register transfer in the vector pipeline operation unit. Therefore, the vector registers 111 and 121 are calculated from the transfer start address specified by the instruction and the number of vector pipeline operation units.
The read address value “8” is calculated and notified to the vector pipeline operation units 110 and 120. Further, in this case, the value of the write start address of the vector registers 112 and 122 is "0".

Of the element data of the vector registers 111 and 121, the element data at the locations indicated by the respective read address registers (not shown) pass through the crossbars 114 and 124 of the pipeline arithmetic units 110 and 120 and write data. It is written to the location of the vector register indicated by the register (not shown). These operations are performed by incrementing the read / write address of the vector register by +1 ((vector length ÷
The number of vector pipeline operation units) is repeated continuously to execute the vector register transfer instruction.

In this way, (transfer start address) mod
When the value of (the number of vector pipeline operation units) is “0”, the instruction can be executed without passing through the register in the crossbar 105 as in the case of executing the transfer instruction between the vector pipeline operation units. It is possible to speed up the transfer instruction of the vector register.

Further, in response to the determination result from the transfer instruction determination means 103, the timing detection means 104 sets the address 0 of the transfer destination vector register in each of the transfer of registers in the vector pipeline operation unit and the transfer of registers between the vector pipeline operation units. The timing at which the element is stored is calculated, and this timing is used as the instruction execution control unit 1.
By notifying 01, it is possible to chain subsequent instructions that had to wait until the end of instruction execution, and speed up.

[0021]

According to the present invention, in a transfer instruction between vector registers, when the value of (transfer start address) mod (the number of vector pipeline operation units) is "0",
The processing can be speeded up by executing the element data transfer in the vector pipeline operation unit.

Further, by calculating the timing at which the vector element at address 0 of the transfer destination vector register is stored for both the transfer in the vector pipeline operation unit and the transfer between the vector pipeline operation units, the subsequent vector instruction is the vector register transfer instruction. When the transfer destination vector register is read and used, chaining is possible and the speed can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a diagram showing an example of a state of transfer source and transfer destination vector registers during vector register transfer.

FIG. 3 is a block diagram showing a conventional example.

[Explanation of symbols]

101, 301 Command control unit 102 Command execution control unit 103 Transfer command determination unit 104 Timing detection unit 105, 114, 124, 305, 314, 324
Crossbar 110, 120, 210, 220, 310, 320
Vector pipeline operation unit 111, 112, 113, 121, 122, 123, 2
11,212,221,222,311,312,31
3,321,322,323 Vector register 115,116,125,126,315,316,3
25,326 arithmetic unit.

Claims (2)

(57) [Claims] 1. A vector processing device comprising a plurality of vector registers, a plurality of vector pipeline operation units having a transfer function between the vector registers, and a crossbar for transferring vector element data between the vector pipeline operation units. According to the value of the transfer start address of the vector register transfer instruction for the element data assigned in order to the plurality of vector pipeline operation units, the element data is used as the element data of another vector register of another vector pipeline operation unit. Will be transported,
A transfer instruction determination means for determining whether or not the vector data is transferred as the element data of another vector register of the own vector pipeline operation unit is provided. In the former case, the read data from the vector pipeline operation unit is the vector pipeline operation unit. Data transfer between the vector registers through the crossbar, and in the latter case, the data transfer function in the vector pipeline arithmetic unit controls the data transfer between the vector registers. A vector processing device characterized by the above. 2. A timing detecting means for calculating the timing stored in the vector register of the vector pipeline arithmetic unit of the transfer destination in each case based on the information from the transfer instruction determining means and notifying the instruction execution control section. 2. The instruction execution control unit controls the execution of the subsequent instruction according to the information from the timing detection means when the subsequent instruction is an instruction for reading the result of the transfer instruction. Vector processing unit.