JPS6357949B2 - - Google Patents

Info

Publication number
JPS6357949B2
JPS6357949B2 JP21013982A JP21013982A JPS6357949B2 JP S6357949 B2 JPS6357949 B2 JP S6357949B2 JP 21013982 A JP21013982 A JP 21013982A JP 21013982 A JP21013982 A JP 21013982A JP S6357949 B2 JPS6357949 B2 JP S6357949B2
Authority
JP
Japan
Prior art keywords
layer
semiconductor
inp
electron
indium
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP21013982A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59100576A (ja
Inventor
Masahiko Takigawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP21013982A priority Critical patent/JPS59100576A/ja
Publication of JPS59100576A publication Critical patent/JPS59100576A/ja
Publication of JPS6357949B2 publication Critical patent/JPS6357949B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/432Heterojunction gate for field effect devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Junction Field-Effect Transistors (AREA)
JP21013982A 1982-11-30 1982-11-30 半導体装置 Granted JPS59100576A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21013982A JPS59100576A (ja) 1982-11-30 1982-11-30 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21013982A JPS59100576A (ja) 1982-11-30 1982-11-30 半導体装置

Publications (2)

Publication Number Publication Date
JPS59100576A JPS59100576A (ja) 1984-06-09
JPS6357949B2 true JPS6357949B2 (fr) 1988-11-14

Family

ID=16584421

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21013982A Granted JPS59100576A (ja) 1982-11-30 1982-11-30 半導体装置

Country Status (1)

Country Link
JP (1) JPS59100576A (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1987003742A1 (fr) * 1985-12-13 1987-06-18 Allied Corporation Dispositif mesfet ayant une couche-barriere de surface semiconductrice
EP0228624B1 (fr) * 1985-12-19 1993-04-21 Sumitomo Electric Industries, Ltd. Transistor à effet de champ
US4962409A (en) * 1987-01-20 1990-10-09 International Business Machines Corporation Staggered bandgap gate field effect transistor
JP2652647B2 (ja) * 1988-01-19 1997-09-10 住友電気工業株式会社 ヘテロ接合電界効果トランジスタ
JP2873583B2 (ja) * 1989-05-10 1999-03-24 富士通株式会社 高速半導体装置

Also Published As

Publication number Publication date
JPS59100576A (ja) 1984-06-09

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