JPS6350736B2 - - Google Patents

Info

Publication number
JPS6350736B2
JPS6350736B2 JP58180004A JP18000483A JPS6350736B2 JP S6350736 B2 JPS6350736 B2 JP S6350736B2 JP 58180004 A JP58180004 A JP 58180004A JP 18000483 A JP18000483 A JP 18000483A JP S6350736 B2 JPS6350736 B2 JP S6350736B2
Authority
JP
Japan
Prior art keywords
ipl
physical address
external storage
selection switch
storage devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58180004A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6072050A (ja
Inventor
Kazuo Shimomichi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58180004A priority Critical patent/JPS6072050A/ja
Publication of JPS6072050A publication Critical patent/JPS6072050A/ja
Publication of JPS6350736B2 publication Critical patent/JPS6350736B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/177—Initialisation or configuration control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
JP58180004A 1983-09-28 1983-09-28 Ｉｐｌ装置選択制御方式 Granted JPS6072050A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58180004A JPS6072050A (ja) 1983-09-28 1983-09-28 Ｉｐｌ装置選択制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58180004A JPS6072050A (ja) 1983-09-28 1983-09-28 Ｉｐｌ装置選択制御方式

Publications (2)

Publication Number Publication Date
JPS6072050A JPS6072050A (ja) 1985-04-24
JPS6350736B2 true JPS6350736B2 (enExample) 1988-10-11

Family

ID=16075768

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58180004A Granted JPS6072050A (ja) 1983-09-28 1983-09-28 Ｉｐｌ装置選択制御方式

Country Status (1)

Country Link
JP (1) JPS6072050A (enExample)

Also Published As

Publication number Publication date
JPS6072050A (ja) 1985-04-24

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