JPS6348122Y2 - - Google Patents

Info

Publication number
JPS6348122Y2
JPS6348122Y2 JP6648682U JP6648682U JPS6348122Y2 JP S6348122 Y2 JPS6348122 Y2 JP S6348122Y2 JP 6648682 U JP6648682 U JP 6648682U JP 6648682 U JP6648682 U JP 6648682U JP S6348122 Y2 JPS6348122 Y2 JP S6348122Y2
Authority
JP
Japan
Prior art keywords
wiring
circuit
bonding pads
region
pellet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP6648682U
Other languages
English (en)
Japanese (ja)
Other versions
JPS58170833U (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1982066486U priority Critical patent/JPS58170833U/ja
Publication of JPS58170833U publication Critical patent/JPS58170833U/ja
Application granted granted Critical
Publication of JPS6348122Y2 publication Critical patent/JPS6348122Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/5445Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/5449Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/547Dispositions of multiple bond wires
    • H10W72/5473Dispositions of multiple bond wires multiple bond wires connected to a common bond pad
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/931Shapes of bond pads
    • H10W72/932Plan-view shape, i.e. in top view
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
JP1982066486U 1982-05-07 1982-05-07 半導体集積回路 Granted JPS58170833U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1982066486U JPS58170833U (ja) 1982-05-07 1982-05-07 半導体集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1982066486U JPS58170833U (ja) 1982-05-07 1982-05-07 半導体集積回路

Publications (2)

Publication Number Publication Date
JPS58170833U JPS58170833U (ja) 1983-11-15
JPS6348122Y2 true JPS6348122Y2 (enExample) 1988-12-12

Family

ID=30076354

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1982066486U Granted JPS58170833U (ja) 1982-05-07 1982-05-07 半導体集積回路

Country Status (1)

Country Link
JP (1) JPS58170833U (enExample)

Also Published As

Publication number Publication date
JPS58170833U (ja) 1983-11-15

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