JPS6345831A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6345831A JPS6345831A JP19080886A JP19080886A JPS6345831A JP S6345831 A JPS6345831 A JP S6345831A JP 19080886 A JP19080886 A JP 19080886A JP 19080886 A JP19080886 A JP 19080886A JP S6345831 A JPS6345831 A JP S6345831A
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxide film
- films
- nitride
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000012535 impurity Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 abstract description 25
- 238000000034 method Methods 0.000 abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 9
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 5
- 239000011574 phosphorus Substances 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 230000002950 deficient Effects 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 229910021339 platinum silicide Inorganic materials 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- -1 boron ions Chemical class 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
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- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特にバイポーラ
トランジスタを含む半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device including a bipolar transistor.
ＬＯＣＯ８法とＤＯＰＯ８法とを利用しフィールドの酸
化膜をマスクとしてベース及びエミッタを形成したバイ
ポーラトランジスタを含む半導体装置の製造方法の従来
例を、以下に説明する。A conventional example of a method for manufacturing a semiconductor device including a bipolar transistor in which a base and an emitter are formed using a field oxide film as a mask using the LOCO8 method and the DOPO8 method will be described below.
第３図１８）〜ｌｄ）は従来の半導体装置の製造方法の
一例を説明するための工程順に示した半導体チップの断
面図である。18) to 1d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an example of a conventional method for manufacturing a semiconductor device.
この従来例は、先ず、第３図（ａ）に示すように、ｐ型
のシリコン基板１上にｎ型のエピタキシャル層２を堆積
し、更にその表面に酸化［３ａ及び３ｂと所定のパター
ンの窒化１１ｇ４ａ及び４ｂを形成して窒化膜４ａ及び
４ｂをマスクとしてＬＯＣＯ８法によりフィールドの酸
化膜５を形成する。In this conventional example, as shown in FIG. 3(a), first, an n-type epitaxial layer 2 is deposited on a p-type silicon substrate 1, and then oxidized [3a and 3b and a predetermined pattern] are formed on the surface of the n-type epitaxial layer 2. Nitride films 4a and 4b are formed, and a field oxide film 5 is formed by the LOCO8 method using the nitride films 4a and 4b as masks.
次に、第３図（ｂ）に示すように、窒化膜４ａを覆うホ
トレジスト膜１３を形成し、ホトレジスト膜１３とフィ
ールド酸化膜５とをマスクとしてホウ素をイオン注入し
てｐ型の不純物層６ｂ′のベースを形成する。Next, as shown in FIG. 3(b), a photoresist film 13 is formed to cover the nitride film 4a, and boron ions are implanted using the photoresist film 13 and the field oxide film 5 as masks to form a p-type impurity layer 6b. ′ form the base.
次に、第３図（Ｃ）に示すように、ホトレジスト膜１３
、窒化１４４ａ及び４ｂ並びに酸化膜３ａ及び３ｂを順
次除去した後、多結晶シリコン嘆を堆積してその上に酸
化膜９ａ 、９ｂ及び９Ｃを介してそれぞれ形成した窒
化膜１０ａ、１０ｂ及び１０ｃをマスクとしてＬＯＣＯ
８法によシフイールドの酸化膜８によって絶縁分離され
た多結晶シリコンｌ１ｇ７ａ。Next, as shown in FIG. 3(C), the photoresist film 13
After sequentially removing nitride films 144a and 4b and oxide films 3a and 3b, polycrystalline silicon film is deposited and nitride films 10a, 10b and 10c formed thereon through oxide films 9a, 9b and 9C are masked. asLOCO
Polycrystalline silicon l1g7a is insulated and isolated by an oxide film 8 of the shield field by the 8 method.
７ｂ及び７Ｃを形成する。7b and 7C are formed.
次に、第３図１ｄｌに示すように、窒化膜ｔＯａ及び１
０ｂ並びに酸化［９ａ及び９ｂを除去した後多結晶シリ
コン膜７ａ及び７ｂを介してエピタキシャル層２及び不
純物層６ｂ′の表面にリン拡散をしてｎ型の不純物層１
１′のコレクタ及び不純物層１２′のエミッタを形成す
る。Next, as shown in FIG. 3 1dl, the nitride films tOa and 1
After removing 0b and oxidation [9a and 9b, phosphorus is diffused into the surfaces of the epitaxial layer 2 and impurity layer 6b' through the polycrystalline silicon films 7a and 7b to form an n-type impurity layer 1.
A collector of impurity layer 1' and an emitter of impurity layer 12' are formed.
この後は窒化膜１０ｃ及び酸化膜９Ｃを除去して、白金
の珪化物のオーミック電極を形成してトランジスタが出
来る。After this, the nitride film 10c and the oxide film 9C are removed, and an ohmic electrode of platinum silicide is formed to complete a transistor.
しかし上述した半導体装置の製造方法は、ベースを形成
した後にその上の窒化膜及び酸化膜をエツチング除去す
るので、その酸化膜除去の時にフィールドの酸化膜のバ
ーズビークの部分が一緒にエツチングされてしまいその
部分のフィールドの酸化膜が薄くなってフィールドの酸
化膜に接したベース接合の深さが非常に浅くなるという
欠点がある。その結果、ベース幅の非常に狭いトランジ
スタが出来てしまい、コレクタ・エミッタ間のパンチス
ルーによって耐圧が低下したりリーク電流が増大するな
どの特性不良によって半導体装置の製造歩留りや品質を
低下させる。However, in the above-described semiconductor device manufacturing method, after forming the base, the nitride film and oxide film on it are etched away, so when the oxide film is removed, the bird's beak portion of the field oxide film is etched together. There is a drawback that the field oxide film in that part becomes thinner and the depth of the base junction in contact with the field oxide film becomes very shallow. As a result, a transistor with a very narrow base width is produced, and the manufacturing yield and quality of semiconductor devices are reduced due to characteristic defects such as a decrease in breakdown voltage and an increase in leakage current due to punch-through between the collector and emitter.
本発明の半導体装置の製造方法は、第１導電型の半導体
基板上に堆積した第２導電型のエピタキシャル層からな
るコレクタ領域の上に酸化膜及び所定のパターンの耐酸
化性膜を順次形成する工程、該耐酸化性膜をマスクとし
て前記コレクタ領域表面を酸化してフィールド絶縁膜を
形成する工程、前記耐酸化性膜及び前記酸化膜を除去し
てベース形成用の窓を開口する工程及び前記フィールド
絶縁膜をマスクとして前記窓のコレクタ領域表面に第１
導電型の不純物を導入してベース領域を形成する工程と
を含み前記ベース領域の前記フィールド絶縁膜に接する
部分が所定の深さを有するトランジスタを形成して成る
。The method for manufacturing a semiconductor device of the present invention includes sequentially forming an oxide film and an oxidation-resistant film in a predetermined pattern on a collector region made of an epitaxial layer of a second conductivity type deposited on a semiconductor substrate of a first conductivity type. a step of oxidizing the surface of the collector region using the oxidation-resistant film as a mask to form a field insulating film; a step of removing the oxidation-resistant film and the oxide film to open a window for forming a base; A first layer is formed on the surface of the collector region of the window using the field insulating film as a mask.
forming a base region by introducing conductivity type impurities, and forming a transistor in which a portion of the base region in contact with the field insulating film has a predetermined depth.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｅ）は本発明の第１の実施例を説明す
るための工程順に示した半導体チップの断面図である。FIGS. 1(a) to 1(e) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a first embodiment of the present invention.
この実施例では、先ず、第１図（ａ）に示すように、ｐ
型のシリコン基板１上に堆積したｎ型のエピタキシャル
層２の表面に約５０ＯＡの酸化膜３ａ及び３ｂ並びに所
定のパターンで膜厚が約１００ＯＡの窒化膜４ａ及び４
ｂを形成し、窒化ｔｆｉ４ａ及び４ｂをマスクとしてＬ
ＯＣＯ８法によりフィールドの酸化膜５を形成する。In this example, first, as shown in FIG. 1(a), p
Oxide films 3a and 3b with a thickness of about 50 OA and nitride films 4a and 4 with a thickness of about 100 OA in a predetermined pattern are formed on the surface of an n-type epitaxial layer 2 deposited on a silicon substrate 1 of the same type.
b, and L using nitrided TFI4a and 4b as masks.
A field oxide film 5 is formed by the OCO8 method.
次に、第１図（ｂ）に示すように、窒化膜４ａ及び４ｂ
並びに酸化膜３ａ及び３ｂを除去した後、フィールドの
酸化膜５をマスクとしてホウ素をエネルギー５０ｋｅＶ
、ドーズ量１０１４ｃｒＩＬ”程度の条件でイオン注入
してｐ型の不純物層６ａ及び６ｂを形成する。Next, as shown in FIG. 1(b), the nitride films 4a and 4b are
After removing the oxide films 3a and 3b, boron was irradiated with an energy of 50 keV using the field oxide film 5 as a mask.
, p-type impurity layers 6a and 6b are formed by ion implantation at a dose of about 1014 crIL''.
次に１第１図（Ｃ）に示すように、多結晶シリコン膜を
５０００Ａ程度被着して、窒化膜１０ａ 、 １０ ｂ
及び１０ｃをそれぞれ酸化膜９ａ 、９ｂ及び９ｃを介
して形成し続いて窒化膜１０ａ、１０ｂ及び１０Ｃをマ
スクとしてＬＯＣＯ８法によシフイールドの酸化膜８に
よって絶縁分離された多結晶シリコン膜７ａ、７ｂ及び
７ｃを形成する。Next, as shown in FIG. 1(C), a polycrystalline silicon film of about 5000A is deposited to form nitride films 10a and 10b.
and 10c are formed through oxide films 9a, 9b, and 9c, respectively, and then polycrystalline silicon films 7a, 7b, and Form 7c.
次に、第１図（ｄ）に示すように、窒化膜１０ａ及び酸
化膜９ａを除去し多結晶シリコン膜７ａを介して９５０
℃、３０分程度の条件でリンを拡散しｎ型の不純物層１
１のコレクタを形成する。Next, as shown in FIG. 1(d), the nitride film 10a and the oxide film 9a are removed, and the polycrystalline silicon film 7a is removed.
℃ for about 30 minutes to form an n-type impurity layer 1.
1 collector is formed.
次に、第１図（ｅ）に示すように１窒化膜１０ｂ及び酸
化膜９ｂを除去し多結晶シリコン［７ｂを介して９５０
℃、１０分程度の条件でリンを拡散しｎ型の不純物層１
２のエミッタを形成する。Next, as shown in FIG. 1(e), the nitride film 10b and the oxide film 9b are removed, and the
℃ for about 10 minutes to form an n-type impurity layer 1.
2 emitters are formed.
以降、窒化膜１０ｃ及び酸化膜９Ｃを除去した後、通常
のプロセスによって白金の珪化物からなるオーミック電
極を形成してトランジスタを備えた半導体装置が出来る
。Thereafter, after removing the nitride film 10c and the oxide film 9C, an ohmic electrode made of platinum silicide is formed by a normal process, thereby completing a semiconductor device including a transistor.
第２図（ａｌ〜（ｅｌは本発明の第２の実施例を説明す
るための工程順に示した半導体チップの断面図である。FIG. 2 (al to (el) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining a second embodiment of the present invention.
この実施例は、第２図（ａ）に示すように、第１の実施
例と同様ＬＯＣＯ８法によシ先ずフィールドの酸化膜５
を形成する。In this embodiment, as shown in FIG. 2(a), a field oxide film 5 is first formed by the LOCO8 method as in the first embodiment.
form.
次に、第２図（ｂ）に示すように、窒化１［４ａ及び酸
化膜３ａを除去し、９５０℃、１０分程度の条件でリン
拡散をしてｎ型の不純物層１１のコレクタを形成する。Next, as shown in FIG. 2(b), the nitride film 4a and the oxide film 3a are removed, and phosphorus is diffused at 950° C. for about 10 minutes to form the collector of the n-type impurity layer 11. do.
次に、第２図（Ｃ）に示すように、窒化膜４ｂ及び酸化
膜３ｂを除去した後、フィールドの酸化膜５をマスクと
してエネルギー５０ ｋｅＶ 、ドーズ量１０に４ｃ！
ＩＬ″−２程度の条件でホウ素をイオン注入しｐ型の不
純物層６ｂのベースを形成する。この時、ｎ型の不純物
層１１のコレクタにもイオン注入されるが注入量が少な
いので相殺されてｐ型にはならない。Next, as shown in FIG. 2(C), after removing the nitride film 4b and the oxide film 3b, using the field oxide film 5 as a mask, an energy of 50 keV and a dose of 10 to 4c!
Boron is ion-implanted under conditions of about IL''-2 to form the base of the p-type impurity layer 6b. At this time, ions are also implanted into the collector of the n-type impurity layer 11, but the amount of implantation is small so it is canceled out. It does not become p-type.
次に、第２図（ｄ）に示すように、第１の実施例同様、
フィールドの酸化膜８で絶縁分離された多結晶シリコン
膜７ａ 、７ｂ及び７Ｃを形成する。Next, as shown in FIG. 2(d), similar to the first embodiment,
Polycrystalline silicon films 7a, 7b and 7C are formed which are insulated and isolated by field oxide film 8.
次に、第２図（ｅ）に示すように、窒化膜１０ａ及び１
０ｂ並びに酸化膜９ａ及び９ｂを除去して、９５０℃、
１０分程度の条件でリン拡散してｎ型の不純物層１２の
エミッタを形成する。Next, as shown in FIG. 2(e), the nitride films 10a and 1
0b and oxide films 9a and 9b, and heated at 950°C.
The emitter of the n-type impurity layer 12 is formed by diffusing phosphorus for about 10 minutes.
以降、通常のプロセスによって白金の珪化物から々るオ
ーミック電極を形成すればトランジスタを備えた半導体
装置が出来る。Thereafter, by forming an ohmic electrode made of platinum silicide using a normal process, a semiconductor device including a transistor is completed.
以上説明したように本発明は、酸化膜を除去した後にフ
ィールドの酸化膜をマスクとしてベースを形成し、その
後はフィールドの酸化膜のバーズビークがエツチングさ
れないので、フィールドの酸化膜に接したベース接合が
十分に深い所に形成されベース幅も大きくとれるため、
パンチスルーによる耐圧低下やリーク電流の増大による
不良が発生しにくく、歩留りが高く高品質のトランジス
。As explained above, in the present invention, after removing the oxide film, the base is formed using the field oxide film as a mask, and since the bird's beak of the field oxide film is not etched after that, the base junction in contact with the field oxide film is Because it is formed deep enough and the base width can be widened,
High-yield, high-quality transistors that are less prone to defects due to a drop in breakdown voltage due to punch-through or an increase in leakage current.
りを含む半導体装置の製造方法が提供できるという効果
がある。The present invention has the advantage that it is possible to provide a method for manufacturing a semiconductor device including the following.
実際に、従来の方法と本発明の方法とによって製造した
トランジスタを比較した結果を、第１表に示す。ここで
、トランジスタの歩留）は５０００個のトランジスタを
並列に接続したときのものである。Table 1 shows the results of comparing transistors actually manufactured by the conventional method and the method of the present invention. Here, the transistor yield is when 5000 transistors are connected in parallel.
及び第２の実施例を説明するための工程順に示した半導
体チップの断面図、第３図ｔａ）〜（ｄ）は従来の半導
体装置の製造方法の一例を説明するための工程順に示し
た半導体チップの断面図である。3(a) to 3(d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the second embodiment, and FIGS. FIG. 3 is a cross-sectional view of the chip.
１・・・・・・シリコン基板、２・・・・・・エピタキ
シャル層、３ａ 、 ３ｂ・・・・・・酸化膜、４ａ、
４ｂ・・・・・・窒化膜、５・・・・・・酸化膜、５
ａ 、 ５ ｂ 、 ６ｂ’・・・−・−不純物層、７
ａ 、 ７ｂ。DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... Epitaxial layer, 3a, 3b... Oxide film, 4a,
4b...Nitride film, 5...Oxide film, 5
a, 5 b, 6b'...-- impurity layer, 7
a, 7b.
７Ｃ・・・・・・多結晶シリコン膜、８ ｔ ９ ａＴ
９ ｂ Ｔ ９ ｃ・・・−ｍ化膜、１０ ａ 、
１０ ｂ 、 １０ Ｃ−・−・・・窒化膜、１１゜１
１’、１２．１２’・・・・・・不純物層、１３・・・
・・・ホトレジスト膜。7C...Polycrystalline silicon film, 8t9aT
9b T9c...-m film, 10a,
10b, 10C---nitride film, 11゜1
1', 12.12'... impurity layer, 13...
...Photoresist film.
Claims (1)
タキシャル層からなるコレクタ領域の上に酸化膜及び所
定のパターンの耐酸化性膜を順次形成する工程、該耐酸
化性膜をマスクとして前記コレクタ領域表面を酸化して
フィールド絶縁膜を形成する工程、前記耐酸化性膜及び
前記酸化膜を除去してベース形成用の窓を開口する工程
及び前記フィールド絶縁膜をマスクとして前記窓のコレ
クタ領域表面に第１導電型の不純物を導入してベース領
域を形成する工程とを含み前記ベース領域の前記フィー
ルド絶縁膜に接する部分が所定の深さを有するトランジ
スタを形成することを特徴とする半導体装置の製造方法
。a step of sequentially forming an oxide film and an oxidation-resistant film in a predetermined pattern on a collector region made of an epitaxial layer of a second conductivity type deposited on a semiconductor substrate of a first conductivity type, using the oxidation-resistant film as a mask; oxidizing the surface of the collector region to form a field insulating film; removing the oxidation-resistant film and the oxide film to open a window for forming a base; and using the field insulating film as a mask to form a collector region in the window. forming a base region by introducing impurities of a first conductivity type into the surface of the region, forming a transistor in which a portion of the base region in contact with the field insulating film has a predetermined depth. Method of manufacturing the device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19080886A JPS6345831A (en) | 1986-08-13 | 1986-08-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19080886A JPS6345831A (en) | 1986-08-13 | 1986-08-13 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6345831A true JPS6345831A (en) | 1988-02-26 |
Family
ID=16264089
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19080886A Pending JPS6345831A (en) | 1986-08-13 | 1986-08-13 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6345831A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53142185A (en) * | 1977-05-18 | 1978-12-11 | Hitachi Ltd | Manufacture of walled emitter type semiconductor device |
-
1986
- 1986-08-13 JP JP19080886A patent/JPS6345831A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53142185A (en) * | 1977-05-18 | 1978-12-11 | Hitachi Ltd | Manufacture of walled emitter type semiconductor device |
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