JPS6344744A - Formation of bump on semiconductor chip - Google Patents
Formation of bump on semiconductor chipInfo
- Publication number
- JPS6344744A JPS6344744A JP61188924A JP18892486A JPS6344744A JP S6344744 A JPS6344744 A JP S6344744A JP 61188924 A JP61188924 A JP 61188924A JP 18892486 A JP18892486 A JP 18892486A JP S6344744 A JPS6344744 A JP S6344744A
- Authority
- JP
- Japan
- Prior art keywords
- protrusion
- inner lead
- semiconductor chip
- bump
- tape carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 230000015572 biosynthetic process Effects 0.000 title description 3
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 23
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 abstract description 12
- 239000002184 metal Substances 0.000 abstract description 12
- 239000011888 foil Substances 0.000 abstract description 6
- 239000002131 composite material Substances 0.000 abstract description 3
- 238000010030 laminating Methods 0.000 abstract description 2
- 239000004411 aluminium Substances 0.000 abstract 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 239000010931 gold Substances 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000002923 metal particle Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000003566 sealing material Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000002604 ultrasonography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体チップのアルミパッドへのバンプ形成方
法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming bumps on aluminum pads of semiconductor chips.
従来の半導体チップへのバンプ形成方法としては、金の
ワイヤーボンディング後金ボールのみをアルミパッド上
に残してワイヤーを切断する方法、アルミパッド上に導
電性ペーストをディス琴ンサーまたは印刷によって塗布
し焼成する方法、金属粒子をアルミパッドに圧着する方
法等が考えられていた。Conventional methods for forming bumps on semiconductor chips include bonding gold wire and then cutting the wire leaving only the gold ball on the aluminum pad, or applying conductive paste onto the aluminum pad using a dispenser or printing and baking it. A method of bonding metal particles to an aluminum pad, etc., had been considered.
〔間誼点を解決するための手段）
しかしながら前述の従来技術において、金のワイヤーボ
ンディングを用いる方法では、バンプを一つ一つ形成す
るため時間がかかる、高密度ピッチのバンプ形成ができ
ない、ワイヤー接断時にボールの根元で安定して接断で
きない等の問題かあ−りた。また導電ペーストを用いる
方法では、ペースト量の制御が難しく安定したバンプ形
成は困難であり、金属粒子の熱ＥＥ着も粒子の供給方法
が難しく実現性に乏しいものであった。[Means for solving the gap point] However, in the conventional technology described above, the method using gold wire bonding takes time to form bumps one by one, cannot form bumps with a high density pitch, and uses wire bonding. There were some problems, such as not being able to stably cut the ball at the base of the ball. Furthermore, in the method using conductive paste, it is difficult to control the amount of paste and stable bump formation is difficult, and thermal EE deposition of metal particles is difficult to implement due to the difficulty in supplying the particles.
そこで本発明はこれらの問題点を解決するもので、その
目的は半導体チップのアルミパッド上に確実かつ迅；速
にバンプを形成する方法を提供するところにある。SUMMARY OF THE INVENTION The present invention is intended to solve these problems, and its purpose is to provide a method for reliably and quickly forming bumps on aluminum pads of semiconductor chips.
本発明は半導体チップへのバンプ形成方法において、テ
ープキャリアのインナーリード上に突起を設ける工程と
、前記半導体チップのアルミパッドに前記インナーリー
ドの前記突起を接合する工程と、前記突起のみを前記ア
ルミパッドに残して前記インナーリードを接続する工程
とを含むことを特徴とする。The present invention provides a method for forming bumps on a semiconductor chip, including a step of providing a protrusion on an inner lead of a tape carrier, a step of bonding the protrusion of the inner lead to an aluminum pad of the semiconductor chip, and a step of bonding only the protrusion to the aluminum pad of the semiconductor chip. The method is characterized in that it includes a step of connecting the inner leads by leaving them on the pads.
第１図（α）〜（ｄ）は本発明の実施例におけろ半導体
チップのアルミパッドへのバンプ形成方法を示す工程図
である。FIGS. 1(α) to 1(d) are process diagrams showing a method for forming bumps on aluminum pads of a semiconductor chip in an embodiment of the present invention.
まず（α）図ではテープキャリア１のインナーリード２
の先端に突起３を形成する。突起３は半導体チップ４の
アルミパッド５に対応した位置に形成される。テープキ
ャリア１としては全面金属のメタルテープでも、絶縁フ
ィルム上に金属箔をラミネートシた複合テープでもよい
。コスト的にはメタルテープの方が安いが、複合テープ
では半導体チップを接合した際に、電気的試験が可能で
ある。金属箔としては通常５５μｍ厚のＣｕ箔を用いる
が、必ツなバンプの高さによって厚みをかえろことも、
また、材質をアルミ等にすることも可能である。突起３
の形成はメツキでも可能であるが、通常はエツチングで
行ない、金ＦＡ箔の一面にインナーリードパターンをも
う一面にバンプパターンをマスキングして両面エツチン
グする。突起３の高さは後工程で接合しやすく、かつ切
断しやすいように金属箔の半分程度、３５μｍ）！８Ｊ
−銅箔であれば１０〜２５μｍとする。またバンプの福
はインナーリードの幅で決まるが、アルミパッドが通常
１００μ属角程度なので、４０〜８０μ虞が望ましい、
また突起３は銅、アルミのままかもしくはアルミと接合
しやすい金属、例えば金、半田等のメツキを施こす、０
〜５μｍのニッケル下地で、０．５〜３μｍの金メツキ
をすることが多い次に（ｂ）図では、前述のテープキャ
リア１のインナーリード２に形成した突起３と、半導体
チップ４のアルミパッド５とを位置合せし、外円が突起
３の外側よりもわずかに大きいヒーターチップ６により
突起３全部を一括して熱圧着する。突起３が金メツキさ
れている場合は、接合条件としては温度が４５０〜６０
０℃、圧力が１端子当り５０〜１５０ｙｒで接合される
。尚必髪によっては超音波を併用することも可能である
。First, in the figure (α), inner lead 2 of tape carrier 1
A protrusion 3 is formed at the tip. The protrusions 3 are formed at positions corresponding to the aluminum pads 5 of the semiconductor chip 4. The tape carrier 1 may be a metal tape made entirely of metal or a composite tape made by laminating metal foil on an insulating film. Metal tape is cheaper in terms of cost, but composite tape allows electrical testing when semiconductor chips are bonded together. Cu foil with a thickness of 55 μm is normally used as the metal foil, but the thickness may be changed depending on the required height of the bump.
It is also possible to use aluminum or the like as the material. Protrusion 3
Although it is possible to form the pattern by plating, it is usually performed by etching, and the inner lead pattern is masked on one side of the gold FA foil and the bump pattern is masked on the other side, and then etched on both sides. The height of the protrusion 3 is about half the height of the metal foil (35 μm) to make it easier to join and cut in the later process! 8J
- If it is a copper foil, the thickness is 10 to 25 μm. Also, the width of the bump is determined by the width of the inner lead, but since aluminum pads are usually around 100μ metallurgy, 40 to 80μ metal width is preferable.
The protrusions 3 may be made of copper or aluminum, or plated with a metal that is easily bonded to aluminum, such as gold or solder.
Gold plating of 0.5 to 3 μm is often performed on a nickel base of ~5 μm. Next, in figure (b), the protrusion 3 formed on the inner lead 2 of the tape carrier 1 described above and the aluminum pad of the semiconductor chip 4 are shown. 5, and all of the protrusions 3 are thermocompression bonded together using a heater chip 6 whose outer circle is slightly larger than the outside of the protrusion 3. If the protrusion 3 is plated with gold, the bonding condition is a temperature of 450 to 60℃.
Bonding is carried out at 0°C and at a pressure of 50 to 150 yr per terminal. In addition, it is also possible to use ultrasound in combination depending on the hair needs.
次に（Ｃ）図ではヒーターチップ６を押しつけたままテ
ープキャリア１を引き上げ、インナーリード２を突起３
の外側で破断する。Next, in figure (C), pull up the tape carrier 1 while pressing the heater chip 6, and insert the inner lead 2 into the protrusion 3.
rupture outside.
その結果（ｄ）図のように半導体チップ４のアルミパッ
ド５上に、突起３を含むインナーリードの先端が接合し
て残り、バンプ７が形成される。As a result, the tips of the inner leads including the protrusions 3 remain bonded to the aluminum pads 5 of the semiconductor chip 4 as shown in FIG.
第２図は第１図で製造された半導体チップ４を回路基板
８にフェイスダウンボンディングで実装し、樹脂封止材
９でモールドした半導体装置１゜の構造を示す断面図で
ある。FIG. 2 is a sectional view showing the structure of a semiconductor device 1° in which the semiconductor chip 4 manufactured in FIG. 1 is mounted on a circuit board 8 by face-down bonding and molded with a resin sealing material 9.
以上述べたように本発明によれば、テープキャリアを使
用する分コストは上がるが、半導体チップの全アルミパ
ッドに一括してバンプを形成することができるため、バ
ンプ形成時間が短かくてすみ、これは特にパッド数の多
い半導体チップに効果が大きい。更に、本発明のバンプ
形成方法はギヤングボンディングと同じＷ、理であるた
め、高密度のバンプ形成が可能であるという効果も有す
るAs described above, according to the present invention, although the cost increases due to the use of a tape carrier, since bumps can be formed on all aluminum pads of a semiconductor chip at once, the bump formation time is shortened. This is particularly effective for semiconductor chips with a large number of pads. Furthermore, since the bump forming method of the present invention uses the same W principle as Guiang bonding, it also has the effect of making it possible to form bumps with high density.
第１図（α）〜（ｄ）は本発明の実施例における半導体
チップへのバンプ形成方法を示す工程図、第２図は第１
図で製造したバンプ付半導体チップを実装した半導体装
置の構造を示す断面図である。
１・・・・・・テ÷プキャリア
２・・・−・・インナーリード
５・・・・・・突 起
４・・・・・・半導体チップ
５・・・・・・アルミパッド
６・・・・・・ヒーターチップ
７・・・・・・バンプ
８・・・・・・回路基板
９・・・・・・樹脂封止材
１０・・・半導体装置
以 上
出願人 セイコーエプソン株式会社
″−３で７題
争乙暑FIGS. 1(α) to (d) are process diagrams showing a method for forming bumps on a semiconductor chip in an embodiment of the present invention, and FIG.
FIG. 2 is a cross-sectional view showing the structure of a semiconductor device mounted with the bumped semiconductor chip manufactured in the figure. 1...Tape carrier 2...Inner lead 5...Protrusion 4...Semiconductor chip 5...Aluminum pad 6... ... Heater chip 7 ... Bump 8 ... Circuit board 9 ... Resin sealing material 10 ... Semiconductor device or more Applicant Seiko Epson Corporation''- 7 issues in 3 Otsuka
Claims (1)
リアのインナーリード上に突起を設ける工程と、前記半
導体チップのアルミパッドに前記インナーリードの前記
突起を接合する工程と、前記突起のみを前記アルミパッ
ドに残して前記インナーリードを切断する工程とを含む
ことを特徴とする半導体チップへのバンプ形成方法。A method for forming bumps on a semiconductor chip includes a step of providing a protrusion on an inner lead of a tape carrier, a step of bonding the protrusion of the inner lead to an aluminum pad of the semiconductor chip, and a step of leaving only the protrusion on the aluminum pad. A method for forming bumps on a semiconductor chip, the method comprising the step of cutting the inner leads by using a wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61188924A JPS6344744A (en) | 1986-08-12 | 1986-08-12 | Formation of bump on semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61188924A JPS6344744A (en) | 1986-08-12 | 1986-08-12 | Formation of bump on semiconductor chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6344744A true JPS6344744A (en) | 1988-02-25 |
Family
ID=16232264
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61188924A Pending JPS6344744A (en) | 1986-08-12 | 1986-08-12 | Formation of bump on semiconductor chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6344744A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006022304A (en) * | 2004-06-08 | 2006-01-26 | Daikin Ind Ltd | Method for producing fluorine-containing elastomer |
| US7538170B2 (en) | 2002-03-14 | 2009-05-26 | Daikin Industries, Ltd. | Fluorocopolymer, process for producing fluorocopolymer, fluorocopolymer curable composition, and cured object |
-
1986
- 1986-08-12 JP JP61188924A patent/JPS6344744A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7538170B2 (en) | 2002-03-14 | 2009-05-26 | Daikin Industries, Ltd. | Fluorocopolymer, process for producing fluorocopolymer, fluorocopolymer curable composition, and cured object |
| EP2085408A1 (en) | 2002-03-14 | 2009-08-05 | Daikin Industries, Ltd. | Fluorocopolymer curable composition, and cured object |
| US7915361B2 (en) | 2002-03-14 | 2011-03-29 | Daikin Industries, Ltd. | Fluorocopolymer, process for producing fluorocopolymer, fluorocopolymer curable composition, and cured object |
| JP2006022304A (en) * | 2004-06-08 | 2006-01-26 | Daikin Ind Ltd | Method for producing fluorine-containing elastomer |
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