JPH0417346A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH0417346A JPH0417346A JP2121492A JP12149290A JPH0417346A JP H0417346 A JPH0417346 A JP H0417346A JP 2121492 A JP2121492 A JP 2121492A JP 12149290 A JP12149290 A JP 12149290A JP H0417346 A JPH0417346 A JP H0417346A
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor chip
- electrode
- lead
- anisotropic conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 88
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000004020 conductor Substances 0.000 claims description 45
- 238000000034 method Methods 0.000 claims description 16
- 238000002788 crimping Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- 229920005989 resin Polymers 0.000 abstract description 14
- 239000011347 resin Substances 0.000 abstract description 14
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 abstract description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052802 copper Inorganic materials 0.000 abstract description 3
- 239000010949 copper Substances 0.000 abstract description 3
- 239000011147 inorganic material Substances 0.000 abstract description 2
- 229910052751 metal Inorganic materials 0.000 abstract description 2
- 239000002184 metal Substances 0.000 abstract description 2
- 239000002923 metal particle Substances 0.000 abstract description 2
- 229910052759 nickel Inorganic materials 0.000 abstract description 2
- 239000011368 organic material Substances 0.000 abstract description 2
- 239000002245 particle Substances 0.000 abstract description 2
- 229910000679 solder Inorganic materials 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 2
- -1 etc. Substances 0.000 abstract 1
- 229910010272 inorganic material Inorganic materials 0.000 abstract 1
- 238000007789 sealing Methods 0.000 description 5
- 238000005452 bending Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000011888 foil Substances 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000004831 Hot glue Substances 0.000 description 1
- 239000004952 Polyamide Substances 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/361—Assembling flexible printed circuits with other printed circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】 以下の順序に従って本発明を説明する。[Detailed description of the invention] The present invention will be described in the following order.
Ａ、産業上の利用分野
Ｂ０発明の概要
Ｃ９従来技術［第４図］
Ｄ１発明が解決しようとする問題点
Ｅ１問題点を解決するための手段
Ｆ１作用
Ｇ、実施例［第１図乃至第３図コ
ａ、半導体装置［第１図、第２図］
ｂ、製造方法［第３図］
Ｈ１発明の効果
（Ａ、産業上の利用分野）
本発明は半導体装置、特に半導体チップの電極をリード
を介して導出する半導体装置とその製造方法に関する。A. Industrial field of application B0 Overview of the invention C9 Prior art [Figure 4] D1 Problems to be solved by the invention E1 Means for solving the problems F1 Effects G. Examples [Figures 1 to 3 Figure a, Semiconductor device [Figures 1 and 2] b, Manufacturing method [Figure 3] H1 Effects of the invention (A, Industrial application field) The present invention leads the way in semiconductor devices, particularly in the electrodes of semiconductor chips. This invention relates to a semiconductor device and a method for manufacturing the same.
（Ｂ、発明の概要）
本発明は、半導体チップの電極をリードを介して導出す
る半導体装置とその製造方法において、半導体チップの
電極とリードとの間の接続に要する時間を短縮し、装置
の肉厚を薄（できるようにし、半導体チップの電極のピ
ッチを小さくできるようにするため、
一方の表面に複数の導体パターン膜が形成された異方性
導電膜を、各導体パターン膜が半導体チップの電極とそ
れに対応したリードとの間を結ぶところに位置するよう
に位置決めした状態で異方性導電膜を半導体チップの電
極及びリードに圧着したものである。(B. Summary of the Invention) The present invention provides a semiconductor device in which electrodes of a semiconductor chip are led out through leads, and a method for manufacturing the same, in which the time required for connection between the electrodes of the semiconductor chip and the leads is shortened, and the device In order to make the wall thickness thinner and to reduce the pitch of the electrodes on the semiconductor chip, an anisotropic conductive film with multiple conductor pattern films formed on one surface is used, each conductor pattern film being attached to the semiconductor chip. An anisotropic conductive film is pressure-bonded to the electrodes and leads of a semiconductor chip, with the anisotropic conductive film positioned so as to connect the electrodes and the leads corresponding to the electrodes.
（Ｃ，従来技術）［第４図］
ＬＳＩ、ＶＬＳ Ｉ等の半導体装置は、一般に、リード
フレームの各ダイパッドに半導体チップをダイボンディ
ングし、半導体チップの各電極とそれに対応するリード
との間を例えば金からなるワイヤによりボンディングし
、樹脂封止後リードフレームを切断するという方法で製
造される。(C, Prior Art) [Figure 4] Semiconductor devices such as LSI and VLSI generally die bond a semiconductor chip to each die pad of a lead frame, and connect each electrode of the semiconductor chip and its corresponding lead. For example, it is manufactured by bonding with gold wire, sealing with resin, and then cutting the lead frame.
第４図はそのような従来の半導体装置の樹脂封止前の状
態を示すものであり、同図において、ａはダイパッド、
ｂ、ｂ・・・・・・はリード、Ｃは銀ペースト等からな
る接着剤、ｄは該接着剤Ｃを介してグイパッドａ上にボ
ンディングされた半導体チップ、ｅ、ｅ・・・・・・は
半導体チップｄの電極、ｆ、ｆ・・・・・・は半導体チ
ップｄの電極ｅ、ｅ、・・・・・・とそれに対応するリ
ードｂ、ｂ、・・・・・・との間を接続するワイヤであ
る。FIG. 4 shows the state of such a conventional semiconductor device before resin sealing, and in the figure, a indicates a die pad;
b, b... are leads, C is an adhesive such as silver paste, d is a semiconductor chip bonded onto the Gui pad a via the adhesive C, e, e... are electrodes of semiconductor chip d, and f, f... are between electrodes e, e,... of semiconductor chip d and their corresponding leads b, b,... This is the wire that connects the.
（Ｄ、発明が解決しようとする問題点）ところで、第４
図に示すような従来の半導体装置には、先ず第１に、ワ
イヤボンディングに要する時間が長くなり、生産性の向
上を阻む要因となるという問題があった。というのは、
ワイヤボンディングは、ワイヤボンダを用いて電極をワ
イヤによりその電極と対応するリードに接続することを
全電極について１個ずつ順番に行うものであり、しかも
多ピン化によって電極の数が数十から口数子ときわめて
多くなっている。従って、１個の半導体チップたりのワ
イヤボンディング時間が無視できない程長くなっている
のである。(D. Problem that the invention attempts to solve) By the way, the fourth problem
The conventional semiconductor device shown in the figure has, first of all, a problem in that the time required for wire bonding is long, which becomes a factor that hinders improvement in productivity. I mean,
Wire bonding uses a wire bonder to connect each electrode with a wire to its corresponding lead, one by one, for all electrodes in turn. Furthermore, as the number of pins increases, the number of electrodes can be reduced from several dozen to just a few. The number of cases has become extremely large. Therefore, the wire bonding time for one semiconductor chip has become so long that it cannot be ignored.
第２に、半導体チップｄの電極ｅとリードｂとの間を接
続するものとして例えば金からなるワイヤｆを用いてお
り、そのワイヤｆはアーチ状に撓む。そしてこの撓みが
樹脂パッケージｇの薄型化を制約する要因になっている
のである。樹脂封止型半導体装置においては、樹脂パッ
ケージの薄型化が強（要求され厚さを１．０ｍｍ以下に
するという要請も生じているので、ワイヤの撓みによっ
て樹脂パッケージの薄型化が制約されるという問題は看
過できないのである。Second, a wire f made of, for example, gold is used to connect the electrode e of the semiconductor chip d and the lead b, and the wire f is bent in an arch shape. This bending is a factor that restricts the reduction in the thickness of the resin package g. In resin-sealed semiconductor devices, there is a strong demand for thinner resin packages (there is also a demand to reduce the thickness to 1.0 mm or less, so the bending of the wires limits the ability to make resin packages thinner). The problem cannot be ignored.
第３に、ワイヤにより電極・リード間を接続する限り、
電極の配置ピッチを飛躍的に小さくすることができない
という問題がある。即ち、ＬＳＩ、ＶＬＳ Ｉの高集積
化の要求はとどまるところを知らないか、その要求に応
えるには多ピン化を図る必要があり、それには電極の配
置ピッチを小さくすることが必要となる。ところが、ワ
イヤボンディングする場合、ボンディングキャピラリを
半導体チップの表面にあてなければならず、隣りの電極
はキャピラリにあたる位置にあってはならない。従って
、電極ピッチを小さ（することがキャピラリによって制
約されるのであり、実際上電極ピッチを１２０μｍ以下
にすることは困難である。Thirdly, as long as wires are used to connect electrodes and leads,
There is a problem in that the arrangement pitch of the electrodes cannot be dramatically reduced. That is, there is no end to the demand for higher integration of LSIs and VLSIs, or to meet this demand it is necessary to increase the number of pins, which requires reducing the arrangement pitch of electrodes. However, when performing wire bonding, the bonding capillary must be placed on the surface of the semiconductor chip, and the adjacent electrode must not be in a position where it comes into contact with the capillary. Therefore, the ability to reduce the electrode pitch is limited by the capillary, and in practice it is difficult to reduce the electrode pitch to 120 μm or less.
尚、ワイアレスボンディング方式としてフリブチツブ方
式、ビームリード方式、フィリームキャリア方式がある
が、いずれもこれ等の各問題を完全に克服しきってはい
ない。Although there are wireless bonding methods such as a flip-chip method, a beam lead method, and a film carrier method, none of these methods has completely overcome these problems.
本発明はこのような問題点を解決すべく為されたもので
あり、半導体チップの電極とリードとの間の接続に要す
る時間を短縮し、装置の肉厚を薄くできるようにし、半
導体チップの電極のピッチを小さくできるようにするこ
とを目的とする。The present invention has been made to solve these problems, and it reduces the time required to connect the electrodes and leads of a semiconductor chip, reduces the thickness of the device, and reduces the thickness of the semiconductor chip. The purpose is to make it possible to reduce the pitch of the electrodes.
（Ｅ、問題点を解決するための手段）
本発明半導体装置は、一方の表面に複数の導体パターン
膜が形成された異方性導電膜を、各導体パターン膜が半
導体チップの電極とそれに対応したリードとの間を結ぶ
ところに位置するようにして異方性導電膜を半導体チッ
プの電極及びリードに圧着したことを特徴とする。(E. Means for Solving Problems) The semiconductor device of the present invention includes an anisotropic conductive film having a plurality of conductor pattern films formed on one surface, each conductor pattern film corresponding to an electrode of a semiconductor chip. The present invention is characterized in that the anisotropic conductive film is pressure-bonded to the electrodes and leads of the semiconductor chip so that the anisotropic conductive film is located at the connection point between the electrodes and the leads.
本発明半導体装置の製造方法は、キャリアフィルム上に
導体膜を形成し、該導体膜をパターニングすることによ
り導体パターン膜を形成し、上記キャリアフィルムの導
体パターン膜が形成された面上に異方性導電膜を形成し
、該異方性導電膜を、各導体パターン膜の半導体チップ
の電極及びリードの端部と対応する位置にてその電極及
びリードの端部に圧着することを特徴とする。The method for manufacturing a semiconductor device of the present invention includes forming a conductor film on a carrier film, forming a conductor pattern film by patterning the conductor film, and applying an anisotropic pattern to the surface of the carrier film on which the conductor pattern film is formed. The method is characterized by forming an anisotropic conductive film, and crimping the anisotropic conductive film to the ends of the electrodes and leads of each conductor pattern film at positions corresponding to the ends of the electrodes and leads of the semiconductor chip. .
（Ｆ、作用）
本発明半導体装置によれば、上面に導体パターン膜が形
成された異方性導電膜を位置決めした状態で、熱圧着す
ることにより半導体チップの各電極とリードとの間を各
導体パターン膜によって電機的に接続することができる
。(F. Effect) According to the semiconductor device of the present invention, the anisotropic conductive film having the conductive pattern film formed on the upper surface is positioned and thermocompression bonded to each other between each electrode and the lead of the semiconductor chip. Electrical connection can be made by the conductive pattern film.
そして、異方性導電膜及びその表面に形成された導体パ
ターン膜により電極・リード間を電気的に接続するので
ワイヤを用いた場合のようにアーチ状に撓むということ
がな（、半導体装置の薄型化を図ることができる。Since the anisotropic conductive film and the conductive pattern film formed on its surface electrically connect the electrodes and leads, there is no possibility of the semiconductor device bending in an arch shape unlike when wires are used. can be made thinner.
本発明半導体装置の製造方法によれば、キャリアフィル
ムをベースにして形成した導体膜のエツチングにより導
体パターン膜を形成し、該導体パターン膜上に異方性導
電膜を塗布し、該異方性導電膜を位置決めして圧着して
略同時に半導体チップの各電極とリードとの間を各導体
パターン膜によって電気的に接続できるので、半導体チ
ップの電極とリードとの間を接続するに要する時間を短
縮することができる。According to the method for manufacturing a semiconductor device of the present invention, a conductor pattern film is formed by etching a conductor film formed based on a carrier film, an anisotropic conductive film is coated on the conductor pattern film, and the anisotropic conductive film is coated on the conductor pattern film. Since the conductive film can be positioned and crimped to electrically connect each electrode of the semiconductor chip and the leads almost simultaneously using each conductive pattern film, the time required to connect the electrodes of the semiconductor chip and the leads can be reduced. Can be shortened.
また、半導体チップの電極とリードとの開をワイヤによ
り接続するわけではないので、キャピラリを全く用いな
い。従って、キャピラリによって電極ピッチが制約され
るということなくなり、電極ピッチを相当に高くするこ
とができ、延いては半導体チップの高集積化が可能にな
る。Further, since the electrodes of the semiconductor chip and the leads are not connected by wires, no capillary is used at all. Therefore, the electrode pitch is no longer restricted by the capillary, and the electrode pitch can be made considerably high, which in turn makes it possible to highly integrate semiconductor chips.
（Ｇ、実施例）［第１図乃至第３図］
以下、本発明半導体装置とその製造方法を図示実施例に
従って詳細に説明する。(G. Embodiment) [FIGS. 1 to 3] Hereinafter, the semiconductor device of the present invention and its manufacturing method will be explained in detail according to the illustrated embodiment.
（ａ、半導体装置）［第１図、第２図］第１図及び第２
図は本発明半導体装置の一つの実施例を示し、第１図は
樹脂封止前の状態を示す断面図、第２図は導体パターン
膜が上面に形成された異方性導電膜の平面図である。(a, semiconductor device) [Figures 1 and 2] Figures 1 and 2
The figures show one embodiment of the semiconductor device of the present invention, FIG. 1 is a cross-sectional view showing the state before resin sealing, and FIG. 2 is a plan view of an anisotropic conductive film with a conductor pattern film formed on the upper surface. It is.
図面において、■はリードフレームのダイパッド、２．
２、・・・・・・はインナーリード、３は例えば銀ペー
ストからなる接着剤で、ダイパッド１に半導体チップ４
を接着している。５は半導体チップ４の表面を覆うパシ
ベーション膜、６．６、・・・・・・は半導体チップ４
の表面に形成されパシベーション膜５の開口を通して露
出する電極パッドである。７は異方性導電膜で、インナ
ーリード２．２、・・・・・・の先端部及び半導体チッ
プ４の各電極パッド６．６、・・・・・・に下面にて熱
圧着により接着されている。８．８、・・・・・・は異
方性導電膜７の上面に形成された導体パターン膜であり
、半導体チップ４の各電極パッド６．６・・・・・・と
それに対応するインナーリード２．２、・・・・・・と
の間を電気的に接続する。具体的には各導体パターン膜
８．８、・・・・・・は、略放射状に形成され、内端部
が各電極パッド６．６、・・・・・・の上方にあたると
ころに位置し、異方性導電膜７の熱圧着により導電性を
有するに至った圧着部を介して電極パッド６．６、・・
・・・・に電気的に接続されている。また、各導体パタ
ーン膜８．８、・・・・・・の外端部は各インナーリー
ド２．２、・・・・・・の先端部の上方にあたるところ
に位置し、異方性導電膜７の熱圧着により導電性を有す
るに至った圧着部を介してインナーリード２．２、・・
・・・・に電気的に接続されている。In the drawing, ■ indicates the die pad of the lead frame; 2.
2, .
is glued. 5 is a passivation film covering the surface of the semiconductor chip 4; 6.6, . . . are the semiconductor chips 4;
This is an electrode pad formed on the surface of the passivation film 5 and exposed through the opening of the passivation film 5. 7 is an anisotropic conductive film, which is bonded to the tips of the inner leads 2.2, . . . and each electrode pad 6.6, . has been done. 8.8, . . . are conductor pattern films formed on the upper surface of the anisotropic conductive film 7, and each electrode pad 6.6, . . . of the semiconductor chip 4 and its corresponding inner The leads 2.2, . . . are electrically connected to each other. Specifically, each conductor pattern film 8.8, . , electrode pads 6.6, .
...is electrically connected to... Further, the outer end of each conductive pattern film 8.8, . . . is located above the tip of each inner lead 2.2, . The inner leads 2.2, . . .
...is electrically connected to...
しかして、半導体チップ４の各電極６．６、・・・・・
・は、異方性導電膜７の圧着部、導体パターン膜８．８
、・・・・・・及び異方性導電膜７の圧着部を介してイ
ンナーリード２．２、・・・・・・に電気的に接続され
ているのである。尚、便宜上樹脂の図示はしないが、第
１図に示す状態で樹脂により封止される。Therefore, each electrode 6.6 of the semiconductor chip 4,...
- is the crimping part of the anisotropic conductive film 7, the conductor pattern film 8.8
, . . . and are electrically connected to the inner leads 2.2, . Although the resin is not shown for convenience, it is sealed with the resin in the state shown in FIG.
このような半導体装置によれば、半導体チップの電極と
リードとの間を電気的に接続する手段としてワイヤーを
用いた半導体装置の場合のようにワイヤがアーチ状に大
きく撓んで樹脂封止した場合における樹脂パッケージの
肉厚を厚（するという虞れがない。According to such a semiconductor device, when the wire is bent greatly in an arch shape and sealed with resin, as in the case of a semiconductor device that uses wire as a means of electrically connecting between the electrode and the lead of the semiconductor chip. There is no risk of increasing the wall thickness of the resin package.
そして、従来のようにワイヤを用いた場合にはボンディ
ング用のキャピラリーでワイヤボンディングを行う関係
から半導体チップの電極バッド６．６、・・・・・・の
配置ピッチを小さくすることが制糺されてしまうが、本
半導体装置によれば、異方性導電膜７上に形成する導体
パターン膜８．８、・・・・・・の加工精度の許す範囲
で電極バッド６．６、・・・・・・の配置ピッチを小さ
くすることができ、該ピッチを１００μｍ以下にするこ
とは容易に為し得る。When wires are used as in the past, it is necessary to reduce the arrangement pitch of the electrode pads 6, 6, etc. of the semiconductor chip because wire bonding is performed using a bonding capillary. However, according to the present semiconductor device, the electrode pads 6.6, . It is possible to reduce the arrangement pitch of . . . and easily reduce the pitch to 100 μm or less.
また、ワイヤは一般に金からなるので、ワイヤボンディ
ング方式の半導体装置はワイヤの材料費が高くなるとい
う問題があるが、本半導体装置にはそのような虞れがな
い。Further, since wires are generally made of gold, wire bonding semiconductor devices have the problem of high wire material costs, but this semiconductor device does not have such a risk.
（ｂ、製造方法）［第３図］
第３図（Ａ）乃至（Ｆ）は第１図及び第２図に示した半
導体装置の製造方法を工程順に示す断面図である。(b. Manufacturing method) [FIG. 3] FIGS. 3(A) to 3(F) are cross-sectional views showing the method for manufacturing the semiconductor device shown in FIGS. 1 and 2 in order of steps.
（Ａ）例えばポリエステルからなる例えば１００μｍ程
度の膜厚のキャリアフィルム９の表面に、膜厚２０μｍ
程度のホットメルト系接着剤［例えばポリアミドフィル
ム（融点約８０℃）。(A) A film having a thickness of 20 μm is applied to the surface of a carrier film 9 made of polyester and having a thickness of about 100 μm, for example.
hot-melt adhesives [e.g. polyamide film (melting point: about 80°C);
尚、後で分離が可能であれば他の材料でも良い。］ １
０を介して例えば銅あるいはアルミニウムからなる導体
箔（厚さ１０〜３０μｍ）１１を接着する。同図（Ａ）
は導体箔１１接着後の状態を示す。Note that other materials may be used as long as they can be separated later. ] 1
A conductor foil 11 made of, for example, copper or aluminum (thickness: 10 to 30 μm) is bonded through the wire. Same figure (A)
shows the state after the conductor foil 11 is adhered.
（Ｂ）次に、上記導体箔１１を選択的にエツチングする
ことにより同図（Ｂ）に示すように導体パターン膜８．
８、・・・・・・を形成する。(B) Next, the conductive foil 11 is selectively etched to form a conductive pattern film 8 as shown in FIG.
8. Form...
（Ｃ）次に、同図（Ｃ）に示すように、キャリアフィル
ム９の表面にペースト状の異方性導電膜７を印刷又はコ
ーティングする。(C) Next, as shown in the same figure (C), a paste-like anisotropic conductive film 7 is printed or coated on the surface of the carrier film 9.
尚、異方性導電膜は、半田、銅あるいはニッケル等の金
属粒子あるいは表面に金属層をコーティングした無機材
料もしくは有機材料からなるところの導電性を有した粒
子を、絶縁性を有する感熱性の樹脂、例えばエポキシ樹
脂中に分散させたものであり、厚さ方向に圧力を印加す
ると厚さ方向に電機的導電性を備えるが、面方向には絶
縁性を有している。The anisotropic conductive film is an insulating, heat-sensitive film that combines electrically conductive particles made of metal particles such as solder, copper or nickel, or inorganic or organic materials whose surfaces are coated with a metal layer. It is dispersed in a resin, for example, an epoxy resin, and when pressure is applied in the thickness direction, it has electrical conductivity in the thickness direction, but has insulating properties in the surface direction.
（Ｄ）次に、表面に導体パターン膜８．８、・・・・・
・を有するキャリアフィルム９を、導体パターン膜８．
８、・・・・・・側の面を下向きにしてグイバッドｌに
半導体チップ４がグイボンディングされたリードフレー
ム上に臨ませる。そして、各導体パターン膜８，８、・
・・・・・の両端部が半導体チップ４の各電極バッド６
．６、・・・・・・及びインナーリド２．２、・・・・
・・の先端部の上方に位置するように位置合せをする。(D) Next, conductor pattern film 8.8 on the surface...
A carrier film 9 having a conductive pattern film 8.
8. With the side surface facing downward, place the Guibad l facing onto the lead frame to which the semiconductor chip 4 is Gui-bonded. Then, each conductor pattern film 8, 8, .
Both ends of each electrode pad 6 of the semiconductor chip 4
．． 6,... and inner lid 2.2,...
Align it so that it is located above the tip of...
その後、ホットツール１２によりキャリアフィルム９の
異方性導電膜７を熱圧着すべき部分を突起部１３．１３
、・・・・・・にて熱圧着する。第３図（Ｄ）は熱圧着
する少し前の状態を小している。Thereafter, using the hot tool 12, the portion of the carrier film 9 where the anisotropic conductive film 7 is to be bonded by thermocompression is attached to the protrusion 13.13.
, . . . for thermocompression bonding. FIG. 3(D) shows the state slightly before thermocompression bonding.
尚、ホットツール１２は例えば１２０〜１６０″Ｃ程度
の温度に加熱されている。Note that the hot tool 12 is heated to a temperature of, for example, about 120 to 160''C.
（Ｅ）熱圧着を終えるとホットツール１２を上昇させて
キャリアフィルム９から離す。第３図（Ｅ）は熱圧着を
終えホットツール１２をキャリアフィルム９から離した
状態を示す。(E) After completing the thermocompression bonding, the hot tool 12 is raised and separated from the carrier film 9. FIG. 3(E) shows the hot tool 12 separated from the carrier film 9 after thermocompression bonding.
（Ｆ）その後、同図（Ｆ）に示すようにキャリアフィル
ム９を異方性導電膜７及び導体パターン膜８．８、・・
・・・・から分離する。すると、第１図に示す半導体装
置が出来上る。その後は、樹脂封止、リードフレームの
不要部分のカットを行えば良い。(F) Thereafter, as shown in FIG.
Separate from... Then, the semiconductor device shown in FIG. 1 is completed. After that, resin sealing and unnecessary portions of the lead frame may be cut.
このように、本半導体装置の製造方法によれば、各導体
パターン膜８．８、・・・・・・の半導体チ・ツブ１の
各電極パッド及び各インナーリード２．２、・・・・・
・の先端への接続を、ホ・ントルー・ン１２＆こてキャ
リアフィルム９を半導体チ・ツブ及びリード２．２、・
・・・・・側へ押圧するという一回の動作で同時に行う
ことかできる。即ち、接続に要する時間を短（すること
ができる。As described above, according to the present semiconductor device manufacturing method, each electrode pad of the semiconductor chip 1 of each conductor pattern film 8.8, . . . and each inner lead 2.2, .・
・ Connect to the tip of the hole 12 & iron carrier film 9 to the semiconductor chip and lead 2.2, ・
...can be done simultaneously in one action of pressing to the side. That is, the time required for connection can be shortened.
尚、半導体装置の製造方法において、半導体チップ４の
電極バッド６．６、・・・・・・と、インナーリード２
．２、・・・・・・との間に高さの差があるので、それ
に応じてホットツール１２の突起１３．１３、・・・・
・・の高さに差を設けたり、あるいはホ・ントツール１
２と、キャリアフィルム９との間に上記高さの差を吸収
することのできるゴム弾性体を介在させるようにしても
良い。In addition, in the method for manufacturing a semiconductor device, the electrode pads 6.6, . . . of the semiconductor chip 4 and the inner leads 2
．． Since there is a height difference between 2, . . . , the protrusions 13 and 13 of the hot tool 12 are adjusted accordingly.
...or set a difference in the height of the tool 1.
A rubber elastic body capable of absorbing the above height difference may be interposed between the carrier film 9 and the carrier film 9.
（Ｈ，発明の効果）
以上に述べたように、本発明半導体装置は、半導体チッ
プの電極とそれに対応するリードの端部との間を接続す
る導体パターン膜が上面に複数本形成された異方性導電
膜を、各導体パターン膜の半導体チップの電極と対応す
る位置にて該電極に圧着し、各導体パターン膜のリード
の端部と対応する位置にて該リードの端部に圧着したこ
とを特徴とするものである。(H, Effect of the Invention) As described above, the semiconductor device of the present invention has a semiconductor device having a plurality of conductor pattern films formed on the upper surface to connect between the electrodes of the semiconductor chip and the ends of the corresponding leads. A directional conductive film was crimped to each conductor pattern film at a position corresponding to the electrode of the semiconductor chip, and to the end of each conductor pattern film at a position corresponding to the end of the lead. It is characterized by this.
従って、本発明半導体装置によれば、上面に導体パター
ン膜が形成された異方性導電膜を位置決めした状態で、
熱圧着することにより半導体チップの各電極とリードと
の間を各導体パターン膜によって電気的に接続すること
ができる。Therefore, according to the semiconductor device of the present invention, with the anisotropic conductive film having the conductive pattern film formed on the upper surface positioned,
By thermocompression bonding, each electrode of the semiconductor chip and the leads can be electrically connected by each conductive pattern film.
そして、異方性導電膜及びその表面に形成された導体パ
ターン膜により電極・リード間を電気的に接続するので
ワイヤを用いた場合のようにアーチ状に撓むということ
がなく、半導体装置の薄型化を図ることができる。Since the anisotropic conductive film and the conductive pattern film formed on its surface electrically connect the electrodes and leads, there is no arch-like bending that occurs when wires are used, and the semiconductor device The thickness can be reduced.
本発明半導体装置の製造方法は、キャリアフィルム上に
導体膜を形成し、該導体膜をパターニングすることによ
り半導体チップの電極とそれに対応するリードの端部を
接続する複数本の導体パターン膜を形成し、上記キャリ
アフィルムの上記導体パターン膜が形成された面上に異
方性導電膜を形成し、上記キャリアフィルム上に形成さ
れた異方性導電８膜を、各導体パターン膜の半導体チッ
プの電極と対応する位置にて該電極に、各導体パターン
膜のリードの端部と対応する位置にて該リードの端部に
、それぞれ圧着し、その後、上記キャリアフィルムを剥
離することを特徴とするものである。The method for manufacturing a semiconductor device of the present invention includes forming a conductor film on a carrier film and patterning the conductor film to form a plurality of conductor pattern films that connect the electrodes of the semiconductor chip and the ends of the corresponding leads. Then, an anisotropic conductive film is formed on the surface of the carrier film on which the conductor pattern film is formed, and the eight anisotropic conductive films formed on the carrier film are applied to the semiconductor chip of each conductor pattern film. The carrier film is crimped to the electrode at a position corresponding to the electrode, and to the end of the lead at a position corresponding to the end of the lead of each conductive pattern film, and then the carrier film is peeled off. It is something.
従って、本発明半導体装置の製造方法によれば、キャリ
アフィルムをベースにして形成した導体膜のエツチング
により導体パターン膜を形成し、該導体パターン膜上に
異方性導電膜を塗布し、該異方性導電膜を位置決めして
圧着することにより略同時に各電極とリードとの間の電
気的接続を行うことができるので、電極とリードとの間
の接続に要する時間を短縮することができる。Therefore, according to the method for manufacturing a semiconductor device of the present invention, a conductor pattern film is formed by etching a conductor film formed based on a carrier film, an anisotropic conductive film is applied on the conductor pattern film, and the anisotropic conductive film is coated on the conductor pattern film. By positioning and press-bonding the oriented conductive film, electrical connections can be made between each electrode and the lead at substantially the same time, so the time required for connection between the electrode and the lead can be shortened.
また、半導体チップの電極とリードとの間をワイヤによ
り接続するわけではないので、キャピラリをボンディン
グに全く用いない。従って、キャピラリによって電極ピ
ッチが制約されるということなくなり、電極ピッチを相
当に高くすることができる。Further, since the electrodes of the semiconductor chip and the leads are not connected by wires, capillaries are not used at all for bonding. Therefore, the electrode pitch is no longer restricted by the capillary, and the electrode pitch can be made considerably high.
第１図及び第２図は本発明半導体装置の一つの実施例を
示すもので、第１図は樹脂封止前における断面図、第２
図は表面に導体パターン膜が形成された異方性導電膜の
平面図、第３図（Ａ）乃至（Ｆ）は第１図及び第２図に
示した半導体装置の製造方法を工程順に示す断面図、第
４図は半導体装置の従来例を示す断面図である。
符号の説明
２・・・リード、４・・・半導体チップ、６・・・電極
、７・・・異方性導電膜、８・・・導体パターン膜、
９・・・キャリアフィルム、
１１・・・導体膜。1 and 2 show one embodiment of the semiconductor device of the present invention, FIG. 1 is a cross-sectional view before resin sealing, and FIG.
The figure is a plan view of an anisotropic conductive film with a conductor pattern film formed on the surface, and Figures 3 (A) to (F) show the manufacturing method of the semiconductor device shown in Figures 1 and 2 in order of steps. 4 is a sectional view showing a conventional example of a semiconductor device. Explanation of symbols 2... Lead, 4... Semiconductor chip, 6... Electrode, 7... Anisotropic conductive film, 8... Conductor pattern film, 9... Carrier film, 11...・Conductor film.
Claims (2)
部との間を接続する導体パターン膜が上面に複数本形成
された異方性導電膜を、各導体パターン膜の半導体チッ
プの電極と対応する位置にて該電極に圧着し、各導体パ
ターン膜のリードの端部と対応する位置にて該リードの
端部に圧着したことを特徴とする半導体装置(1) An anisotropic conductive film with a plurality of conductive pattern films formed on the top surface that connects the electrodes of the semiconductor chip and the ends of the corresponding leads, each of which corresponds to the electrode of the semiconductor chip. A semiconductor device characterized in that the conductor pattern film is crimped to the electrode at a position corresponding to the end of the lead of each conductive pattern film at a position corresponding to the end of the lead.
膜をパターニングすることにより半導体チップの電極と
それに対応するリードの端部との間を接続する複数本の
導体パターン膜を形成し、上記キャリアフィルムの上記
導体パターン膜が形成された面上に異方性導電膜を形成
し、上記キャリアフィルム上に形成された異方性導電膜
を、各導体パターン膜の半導体チップの電極と対応する
位置にて該電極に、各導体パターン膜のリードの端部と
対応する位置にて該リードの端部に、それぞれ圧着し、
その後、上記キャリアフィルムを剥離することを特徴と
する半導体装置の製造方法(2) forming a conductor film on the carrier film and patterning the conductor film to form a plurality of conductor pattern films connecting between the electrodes of the semiconductor chip and the ends of the corresponding leads; An anisotropic conductive film is formed on the surface of the carrier film on which the conductor pattern film is formed, and the anisotropic conductive film formed on the carrier film corresponds to the electrode of the semiconductor chip of each conductor pattern film. crimping the conductor pattern film to the electrode at a position corresponding to the end of the lead at a position corresponding to the end of the lead of each conductor pattern film;
A method for manufacturing a semiconductor device, the method comprising: thereafter peeling off the carrier film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2121492A JP2785441B2 (en) | 1990-05-11 | 1990-05-11 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2121492A JP2785441B2 (en) | 1990-05-11 | 1990-05-11 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0417346A true JPH0417346A (en) | 1992-01-22 |
| JP2785441B2 JP2785441B2 (en) | 1998-08-13 |
Family
ID=14812505
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2121492A Expired - Fee Related JP2785441B2 (en) | 1990-05-11 | 1990-05-11 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2785441B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0786808A1 (en) * | 1996-01-19 | 1997-07-30 | Shinko Electric Industries Co. Ltd. | Anisotropic conductive sheet and printed circuit board |
-
1990
- 1990-05-11 JP JP2121492A patent/JP2785441B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0786808A1 (en) * | 1996-01-19 | 1997-07-30 | Shinko Electric Industries Co. Ltd. | Anisotropic conductive sheet and printed circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2785441B2 (en) | 1998-08-13 |
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