JPS6343939B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frame synchronization detection circuit, and in particular to a method for efficiently using frame memory for distributed frame patterns to perform multi-point monitoring of frame patterns and shorten synchronization recovery characteristics. Regarding.

As a conventional distributed frame synchronization detection circuit,
There is a method in which the synchronization pattern is detected bit by bit as an individual synchronization signal, and a method in which a frame memory corresponding to the number of synchronization bits is used to monitor multiple points, but the former requires a longer synchronization pull-in time in principle. The latter method has the disadvantage that although synchronization is faster, the memory capacity for the frame memory becomes larger.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks by using a relatively small frame memory, detecting frame synchronization by equivalently monitoring multiple points, and providing an inexpensive frame synchronization method with good synchronization recovery characteristics.

The present invention detects a plurality of frame pattern bits simultaneously by storing an input signal in a part of the memory of a relatively small frame, and stores the detection results and other intermediate results in a frame memory. Multi-point monitoring of distributed frame patterns can be performed by detecting frame synchronization and creating new intermediate results from the detection intermediate results of previous frame pattern bits, and storing them in the frame memory for storing intermediate results. It was designed so that

Below, as an example of the present invention, PCM primary group (type 24)
This section describes a method for detecting frame synchronization patterns. FIG. 1 shows the frame synchronization pattern of the PCM primary group, and the frame synchronization pattern is of a distributed arrangement type in which 1 bit appears every 193 bits. Strictly speaking, the positions marked with ○ in the figure are frame synchronization patterns, and the positions marked with triangles are multiframe synchronization patterns, but a method for detecting frame synchronization patterns using these together will be explained. (At this time, the multi-frame synchronization pattern will also be detected at the same time.) The x mark is a bit for game alarm and has no relation to the synchronization pattern.
But 1 is fine. FIG. 2 is a diagram illustrating the operating principle of the embodiment of the present invention. In the figure, A is a frame memory circuit for storing input signals and intermediate detection results, and B is a decoder that outputs the final detection results and intermediate results from the output of the frame memory.
The frame synchronization pattern (10001101110×) in Figure 1 is 011 where 100 is A and 011 is B.
Divide into four groups, with C being C and 10× being D.
In FIG. 2, numerals 1 to 8 indicate 193-bit shift registers. When input data comes in from the input, the input bits and the bits from two frames before and one frame before are output to the honeycomb by means of 7 and 8. Het is a terminal that outputs a coded signal of the result detected by Honeyho, Iro is a terminal that inputs the result output from Het to B after 3 frame bits, and H is a terminal that outputs the result of whether synchronization has been detected. It is. Third
FIG. 4 shows a flowchart explaining the operating principle procedure of the present invention, and FIG. 4 shows a truth table explaining the input/output logic of the decoder of FIG. 2. As shown in Figures 3 and 4, the code representing the intermediate result outputted is 0,1 if the alphabet is 0,0 and the honey is A, and the code is 0,1, depending on the detection result of the alphabet. If Honeyho is B, then 1,0, Iro is 1,0, and Honeyho is C, then 1,1, A, Ro, is 1,1, and Honeyho is D, then synchronization is detected.Only in this case Output Chihe1. If the above conditions are not met, 0,0 is output. Here, the third digit of D is not related to the frame synchronization bit, so it may be 1, 0, 0 or 1, 0, 1. Next, the flow of synchronization detection will be explained with reference to FIG. The frame synchronization patterns are A, B, C, and D, so all you have to do is find them. If A is detected, it will output 0, 1, and then after 3 frames, it will output 0, 1, and so on.
When 1 appears and A and B are 0 and 1, it indicates that A was detected three frame bits ago. If B is detected at C, N, and E, then Outputs 1,0. This means that B has been detected after A. If neither A nor B is detected, then
Outputs 0,0, to the output. If A is detected,
Since the first detected A is not the frame synchronization bit A, 0 and 1 are output to the bottom and the next bit is detected, and the rest is the same as when A was detected for the first time. When A and B are 1 and 0, it means that B was detected after A three frame bits ago, and if C is detected at C, D, and E, then H, G is 1,
Outputs 1. This means that A, then B, and then C are detected. If neither C nor A is detected, let H, G be 0,0. If A is detected, the previously detected A and B are not frame synchronization bits, so the flow is the same as when A was detected for the first time.If A and B are 1, 1, then up to 3 frames ago. This shows that B is detected next to A, and then C is detected, and if D is detected in C, D, and E,
This means that B is detected next to A, then C is detected, and then D is detected, so that synchronization is detected and 1 is output to H, and at the same time, the presence or absence of detection of A is output to H and F. If neither D nor A is detected, then 0,
0, and starts synchronization detection from the beginning.
However, if D has the same symbol as A, this A may be the first A for synchronization detection. That is, A, B,
In the case of C, A, B, C, D, the first A,
Although synchronization is detected at B, C, and A, 1 is sent to H, which means that pseudo synchronization has been detected. This cannot be avoided even when using a conventional frame memory that views 12 bits at a time. The above algorithm utilizes the fact that A≠B and A≠C.

As described above, the present invention blocks multi-bit frame synchronization bits, performs synchronous multi-point monitoring of each block, and encodes the detection results of each block up to that point, thereby reducing the number of frame memories required and facilitating comparison. This is very effective because it allows equivalent multi-point monitoring with a small frame memory and a short synchronization recovery time.

[Brief explanation of drawings]

Figure 1 is a multi-frame configuration diagram of the PCM primary group.
FIG. 2 is a block configuration diagram explaining the operating principle of the present invention, and FIG. 3 is a flow diagram explaining the procedure of the operating principle of the present invention. FIG. 4 is a truth table explaining the input/output logic of the decoder of FIG. 2.

Claims (1)

[Claims] 1 Frame synchronization patterns ◎, △,
means for outputting the parallel pattern (C, D, E) as an input signal (H, G) encoded according to a predetermined logical relationship;
a decoder B that outputs a Frame synchronization detection characterized in that by determining the logical relationship and detecting that the input order of the parallel patterns is a predetermined one, a synchronization signal (ch) is output and a distributed frame pattern is detected. circuit.