JPS62176851A - Script character generating circuit - Google Patents

Script character generating circuit

Info

Publication number
JPS62176851A
JPS62176851A JP61018889A JP1888986A JPS62176851A JP S62176851 A JPS62176851 A JP S62176851A JP 61018889 A JP61018889 A JP 61018889A JP 1888986 A JP1888986 A JP 1888986A JP S62176851 A JPS62176851 A JP S62176851A
Authority
JP
Japan
Prior art keywords
output
circuit
character pattern
script
control signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61018889A
Other languages
Japanese (ja)
Inventor
Isao Murakami
功 村上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61018889A priority Critical patent/JPS62176851A/en
Publication of JPS62176851A publication Critical patent/JPS62176851A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K15/00Arrangements for producing a permanent visual presentation of the output data, e.g. computer output printers
    • G06K15/02Arrangements for producing a permanent visual presentation of the output data, e.g. computer output printers using printers

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Dot-Matrix Printers And Others (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

PURPOSE:To make it possible to generate a script character without increasing the capacity of a character pattern memory, by shifting the output of a change- over gate by one bit in response to a control signal and applying OR operation to the mutually corresponding bits of said shift output and the output of the change-over gate. CONSTITUTION:When a script character is generated, that is, when a control signal C is a logical value '1', the parallel output data O1-O24 of an OR circuit 3 are outputted as a logical value '0'. Further, the output of the OR circuit 3 receives each bit operation in a change-over gate 4, a shift circuit 5 and an OR circuit 6 to output data O25-O40. When a character having a normal size is outputted, the control signal C goes to a logical value '0' and the parallel output b1-b40 of a register 2 are outputted as output data O1-O40 as they are. By this method, because the script character pattern can be generated from a character pattern memory, the capacity of the memory can be reduced.

Description

【発明の詳細な説明】 第1図を参照すると、図示せぬマイクロプロセッサに含
まれる文字パターンメモリ1には、通常の大ぎさく本実
施例では40ビット)の文字パターンが記憶されている
。文字パターンメモリ1に記憶されている文字パターン
データは、メモリ読出制御回路(図示ぽず)からの制御
により読出されレジスタ2にラッチされる。レジスタ2
からの40ビットの並列文字パターンデータb1〜b4
0は、互いに相隣り合う2ビット(blとb2.b3と
b4.・・・・・・、b39とb40)毎に論理和回路
3に入力される。論理和回路3からの下位の並列16ビ
ットスクリプト文字パターンデータは、レジスタ3の出
力データb25〜b40と切換ゲート4において制御信
号Cに応じて切換えられ、データa25〜a40として
出力される。
DETAILED DESCRIPTION OF THE INVENTION Referring to FIG. 1, a character pattern memory 1 included in a microprocessor (not shown) stores a normal character pattern (40 bits in this embodiment). Character pattern data stored in character pattern memory 1 is read out and latched in register 2 under control from a memory read control circuit (not shown). register 2
40-bit parallel character pattern data b1 to b4 from
0 is input to the OR circuit 3 for every two adjacent bits (bl, b2, b3, b4, . . . , b39, b40). The lower parallel 16-bit script character pattern data from the OR circuit 3 is switched according to the output data b25 to b40 of the register 3 and the control signal C at the switching gate 4, and output as data a25 to a40.

このデータa25〜a40は1ビットシフト回路5へ入
力されて、データa40がa39.・・・・・・データ
a26がa25となるように1ビットづつシフトされる
These data a25 to a40 are input to the 1-bit shift circuit 5, and data a40 is changed to a39. ...Data a26 is shifted one bit at a time so that it becomes a25.

このシフト出力と切換えゲート4の出力a25〜a40
とがビット対応毎に論理和回路6にて論理和演算される
。この論理和演算出力が40ビットの出力のうち下位1
6ビット出力データ025〜Q40となる。上位24ビ
ット出力データは切換えゲート4の上位24ビットデー
タ01〜024である。
This shift output and the outputs a25 to a40 of the switching gate 4
are logically summed in the logical sum circuit 6 for each bit correspondence. This OR operation output is the lower 1 of the 40 bits of output.
The result is 6-bit output data 025 to Q40. The upper 24-bit output data is the upper 24-bit data 01 to 024 of the switching gate 4.

スクリプト文字を発生する場合、すなわち制御信号Cが
論理値「1」の場合には、論理和回路3の並列出力デー
タ01〜024が論理値rOJとして出力される。更に
、出力データ025〜040としては、論理和回路3の
出力が切換ゲート4.シフト回路5及び論理和回路6に
おける各ビット操作を受けて出力される。
When a script character is generated, that is, when the control signal C has a logical value of "1", the parallel output data 01 to 024 of the OR circuit 3 are output as the logical value rOJ. Furthermore, as output data 025 to 040, the output of the OR circuit 3 is output to the switching gate 4. Each bit is manipulated by the shift circuit 5 and the OR circuit 6 and output.

通常の大きさの文字を出力する場合には、制御信号Cが
論理値「0」となり、レジスタ2の並列出力b1〜b4
0がそのまま出力データ01〜34Gとして出力される
When outputting characters of normal size, the control signal C becomes a logic value "0", and the parallel outputs b1 to b4 of the register 2
0 is output as is as output data 01 to 34G.

文字パターンメモリ1に、第2図に示すような縦40ビ
ットの文字パターンが記憶されている場合、上から8ビ
ットずつ5バイトのデータとしてレジスタ2にラッチさ
れる。このとき、制御信号Cが論理値「0」であれば、
論理和n路3の各オアゲートの出力は禁止され、またシ
フドロ路5のアンドゲートの出力も禁止されるので、レ
ジスタ2の各ビット出力がそのまま出力データ01〜0
40となり、第2図の文字パターンが得られる。
When the character pattern memory 1 stores a 40-bit vertical character pattern as shown in FIG. 2, the upper 8 bits are latched into the register 2 as 5-byte data. At this time, if the control signal C has a logical value of "0",
The output of each OR gate of the logical sum path 3 is prohibited, and the output of the AND gate of the shift path 5 is also prohibited, so each bit output of the register 2 becomes the output data 01 to 0 as it is.
40, and the character pattern shown in FIG. 2 is obtained.

制御信号Cが「1」の場合、レジスタ2の隣接2ビット
同士が論理和演算され、出力データ01〜024及びa
25〜a4Gにより得られる文字パターンは第3図のご
ときスクリプト文字となる。更に当該出力データのうち
a25〜a4Gはシフト回路5にて1ビットずつ順次シ
フトされ、このシフト出力とデータa25〜a40とが
論理和回路6にて論理和演算されて結果的に第4図に示
すスクリプト文字パターンが得られる。このスクリプト
文字パターンは、線の太さが通常の第2図の文字パター
ンと同一となるという効果を有している。
When control signal C is "1", two adjacent bits of register 2 are logically ORed, and output data 01 to 024 and a
The character pattern obtained from 25 to a4G becomes a script character as shown in FIG. Further, among the output data, a25 to a4G are sequentially shifted one bit at a time by a shift circuit 5, and this shift output and data a25 to a40 are ORed by an OR circuit 6, resulting in the data shown in FIG. You will get the script character pattern shown below. This script character pattern has the effect that the line thickness is the same as the normal character pattern shown in FIG.

尚、通常の文字パターンの上半分に圧縮されたスクリプ
ト文字パターンを得る場合には、上位ビットに対して同
様なビット操作をすれば良いことは明白である。
It should be noted that in order to obtain a script character pattern compressed into the upper half of a normal character pattern, it is obvious that similar bit operations can be performed on the upper bits.

11立皇j 以上説明したとおり、本発明によれば、通常の大きさの
文字パターンを記憶した文字パターンメモリからスクリ
プト文字パターンを発生することができるので、スクリ
プト文字用のスクリプト文字パターンメモリを用意する
必要がなく、メモリ容量を削減できる。また、スクリプ
ト文字の線幅が通常の文字のそれに対して何等変化しな
いという特有の効果もある。
As explained above, according to the present invention, a script character pattern can be generated from a character pattern memory that stores character patterns of normal size, so a script character pattern memory for script characters is prepared. memory capacity can be reduced. There is also the unique effect that the line width of script characters does not change in any way compared to that of normal characters.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例のブロック図、第2図〜第4
図は本発明の詳細な説明するための通常の大きさの文字
パターン及びスクリプト文字パターンを示す図である。 主要部分の符号の説明 1・・・・・・文字パターンメモリ 2・・・・・・レジスタ 3.6・・・・・・論理和回路 4・・・・・・切換ゲート 5・・・・・・シフト回路
FIG. 1 is a block diagram of an embodiment of the present invention, and FIGS.
The figure is a diagram showing a normal size character pattern and a script character pattern for explaining the present invention in detail. Explanation of symbols of main parts 1...Character pattern memory 2...Register 3.6...OR circuit 4...Switching gate 5...・Shift circuit

Claims (1)

【特許請求の範囲】[Claims] 文字パターンメモリからの複数ビットの並列出力データ
の互いに相隣り合う2ビット毎に論理和演算する論理和
回路と、前記文字パターンメモリの出力及び前記論理和
回路の出力を制御信号に応じて択一的に導出する切換ゲ
ートと、前記切換ゲートの出力を前記制御信号に応じて
1ビットシフトするシフト回路と、このシフト出力と前
記切換ゲート出力との互いに対応するビットとを論理和
演算する論理和回路とを有することを特徴とするスクリ
プト文字発生回路。
an OR circuit that performs an OR operation for every two adjacent bits of multiple bits of parallel output data from a character pattern memory; and an output of the character pattern memory and an output of the OR circuit that are selected according to a control signal. a shift circuit that shifts the output of the switching gate by one bit in response to the control signal; and a logical sum that performs a logical OR operation on mutually corresponding bits of the shift output and the switching gate output. A script character generation circuit comprising a circuit.
JP61018889A 1986-01-30 1986-01-30 Script character generating circuit Pending JPS62176851A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61018889A JPS62176851A (en) 1986-01-30 1986-01-30 Script character generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61018889A JPS62176851A (en) 1986-01-30 1986-01-30 Script character generating circuit

Publications (1)

Publication Number Publication Date
JPS62176851A true JPS62176851A (en) 1987-08-03

Family

ID=11984133

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61018889A Pending JPS62176851A (en) 1986-01-30 1986-01-30 Script character generating circuit

Country Status (1)

Country Link
JP (1) JPS62176851A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7394582B2 (en) 1999-09-09 2008-07-01 Fuji Xerox Co., Ltd. Rotary deflector, optical scanning unit and image forming apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7394582B2 (en) 1999-09-09 2008-07-01 Fuji Xerox Co., Ltd. Rotary deflector, optical scanning unit and image forming apparatus

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