JPH0264874A - Picture memory control circuit - Google Patents

Abstract

PURPOSE:To improve the processing speed of data editing for a picture memory by writing the data of the positions from the most significant bit to an optional bit of one word of write data in the addresses of the picture memory from an optional bit address by replace designation. CONSTITUTION:A first pattern generator 24 which generates the pattern of one word length where a signal '0' continues by a number equal to the value of a bit address stored in a bit address counter 14 and the rest consisting of the signal '1' is provided. Besides, a second pattern generator 29 which generates the pattern of one word length where the signal '1' continues by the number of bits stored in a bit length register 18 and the rest is expressed by the signal '0' is provided. Then, a continuous bit string from the most significant bit to an optional bit position in the one word of the write data is written in the addresses of the picture memory from the optional bit address by the replace designation. Thus, the processing quantity of a control processor can be reduced, and the processing speed at the time of the editing of the data to the picture memory can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Second Industrial Fields] The present invention relates to a control circuit for an image memory used in a dot matrix display device used as an output device for information processing.

2. Prior Art] In an IJ hook type display device, data to be displayed is stored in an image memory and controlled by an image memory control circuit. In such a conventional image memory control circuit, for example, when character data of 24x24 dots is stored in an image memory of 16 bits per word, the address of an arbitrary bit shifted from the word boundary of the image memory is stored. Normally, a processing function is provided that allows data to be written with a replace designation (overwrite designation).

For example, if a 16x16 dot character is simply enlarged to create a 24x24 dot character, the diagonal lines of the character cannot be clearly expressed. Therefore, in order to express this part smoothly, there are cases where display data is corrected only in the corresponding area of the character.

In such a case, the simple replace specification described above cannot be used. Conventionally, in such a case, a control processor performs a logical operation on read data and write data from the image memory using pattern data in which necessary bits are masked. Then, a process is performed in which data is embedded with a continuous pit string from an arbitrary bit position of read data to an arbitrary bit position (most significant via of write data), and written into an image memory.

[Problem to be solved by the invention]

However, such processing places a burden on the control processor, resulting in a problem that the processing speed of data editing for the image memory becomes slow.

Therefore, an object of the present invention is to write continuous pits (from the most significant bit to an arbitrary bit position in one word of write data) from an arbitrary bit address in the image memory without placing a burden on the control processor. An object of the present invention is to provide an image memory control circuit that can perform writing with replacement designation.

[Means to solve the problem]

In the present invention, the image memory control circuit is provided with the following circuits.

(b) A word address counter that stores the word address of the image memory.

(b) A pit address counter that stores the bit address of the image memory.

(c) Write data register that stores write data to image memory.

(d) A bit length register that stores the bit length from the most significant bit of write data to an arbitrary bit position.

(e) A first barrel shifter that shifts write data by a number equal to the value of the bit address.

1) A first pattern generator that generates a 1-word-length pattern consisting of a number of consecutive "0" signals equal to the value of the bit address, and the remaining signals "1°."

(g) The signal “1” continues for the number of bits stored in the bit length register, and the rest are 1s represented by the signal “0”.
A second pattern generator for generating word-length patterns.

(H) A second barrel shift for shifting the pattern output from the second pattern generator by a number equal to the value of the bit address.

(2) A knot circuit that inverts the signal "1" and the signal "0'' in the pattern output from the first pattern generator.

(j) A first selector circuit that selects one of the output of the first pattern generator and the output of the knot circuit.

(l) A first AND circuit that calculates the AND of the first select circuit and the output of the second barrel shifter.

(w) A second AND circuit that takes the logical product of the output of the first AND circuit and the output of the first barrel shifter.

(W) A third AND circuit that calculates the logical product of the pattern obtained by inverting the signal "1" and the signal "0" at the output of the first AND circuit and the data read from the image memory.

(Power) A logical operation circuit that performs logical operations on the outputs of the second AND circuit and the third AND circuit.

(Y) An adder that adds the bit address value and the bit length value stored in the bit length register, and outputs a signal that becomes active when the addition result is a value of 16 or more.

In the present invention, data from the most significant bit to an arbitrary bit position in one word of write data is written with replacement specified from an arbitrary bit address in the image memory.

〔Example〕

The present invention will be described in detail below with reference to Examples.

FIG. 1 shows an image memory control circuit and an image memory controlled by the image memory control circuit in one embodiment of the present invention.

The image memory control circuit 11 of this embodiment includes an image memory 1
It is provided with two types of counters: a word address counter 13 for storing two word addresses, and a bit address counter 14 for storing bit addresses. The output signal 15 of the word address counter 13 is supplied to the address terminal A of the image memory 12.

The image memory control circuit 11 also controls these counters 13.
．． There are three types of registers: a write data register 17, a bit length register 18, and a mode register 19 connected to the same data supply source as 14. Among these, the write data register 17 is a register that stores write data to the image memory 12. The bit length register I8 stores the bit length of data to be written into the image memory 12 from the most significant bit to an arbitrary bit position. The mode register 19 is connected to a logic operation circuit 2 which will be explained later.
This is a register that sets the type of logical operation performed in 1.

A first barrel shifter 23 is provided on the output side of the write data register 17 for shifting the write data by a number equal to the bit address value. A first pattern generator 24 is provided on the output side of the bit address counter 14.

The first pattern generator 24 is a generator that generates a one-word-length pattern in which the number of consecutive "0"s equal to the bit address value is represented by "1"s, and the rest are represented by "1"s. The output of the first pattern generator 24 is input to one input terminal of the first selector circuit 25, and is also input to the first knot circuit 26, where the "1" and "0" of the one word length pattern described above are input. A reversed pattern is created.

The created inversion pattern is input to the other input terminal of the first selector circuit 25. The first select circuit 25 is
One of these patterns is selected and the selection result is supplied to one terminal of the first AND circuit 27.

On the other hand, on the output side of the bit length register 18, a second
A pattern generator 29 is provided. The second pattern generator 29 uses the bit length register 18
A 1-word length pattern is generated in which the number of bits stored in ``1'' is consecutive and the remaining bits are 0''.The output side of the second pattern generator 29 stores the output 1-word length pattern as a bit address value. A second barrel shifter 31 is provided to shift the barrel by a number equal to .

The output of the second barrel shifter 31 is supplied to the other terminal of the first AND circuit 27. The first AND circuit 27 performs a logical product of both terminals and supplies the result to the second AND circuit 32 and the second NOT circuit 33. The logic result of the second AND circuit 32 is supplied to the logic and arithmetic circuit 21 described above. The second NOT circuit 33 inverts 0" and "1" at the output of the first AND circuit 27. This inversion result is supplied to one input terminal of the third AND circuit 35. The other input terminal of the AND circuit 35 is supplied with the output signal of the read data register 36 that stores the data read from the data terminal of the image memory 12, and here the logical product of the two is performed. is now being taken.

This logic result is supplied to the logic operation circuit 21, and a predetermined logic operation is performed together with the logic result of the second AND circuit 32. The result of this logical operation is stored in the buffer 37, then output to the data bus 38, and is sent to the image memory 1.
2 data terminals.

Further, the adder 39 outputs the bit address value output from the bit address counter 14 and the bit length register 1.
and the bit length value output from 8. A carry signal 41 that becomes active is output when the result of this addition exceeds the numerical value "16".

This carry signal 41 is supplied to a timing circuit 43. The timing circuit 43 includes the first selector circuit 25,
Signals 44, 45, and 46 are supplied to read data register 36 and buffer 37, respectively.

By the way, FIG. 2 shows write data written to the image memory. In the image memory 12 shown in FIG. 1, data having a 4-bit×4-bit structure as shown in FIG. 2(A) is written as one word (-16 bits). FIG. 2B shows each bit from "a" to "p" serially.

On the other hand, FIG. 3 shows a state in which write data is written from bit address Do in word address N of image memory 12.

The actual operation of the image memory control circuit shown in FIG. 1 will now be described based on FIGS. 2 and 3.

First, the word address counter 13 stores the word address N.
is set, and the bit address DH is set in the bit address counter 14. Also, write data register 17
1 expressed as write data (abcdefghijklmnop) in
Word data is set and bit length register 1
Bit length “4” to be written in write data to 8
is set. At this time, the mode register 19 is set to the OR mode.

Once the above settings have been made, startup for writing to the image memory 12 is performed.

At this time, the timing circuit 43 first executes a successive cycle on the image memory 12 by starting this writing.

As a result, data is read from the word address N shown in FIG.
6.

On the other hand, the first pattern generator 24 generates a pattern (0000!) in which the same 13-bit (Dl!) "0" as the bit address value is consecutive and the remaining 3 bits are "1".
000000000111). The second pattern generator 29 generates a pattern (111100000000000) in which 4 bits equal to the bit length value are consecutively "1"s and the rest are 0s.

This pattern is shifted by 13 bits by the second barrel shifter 31, and the pattern (1000000000001
11) It becomes.

The first selector circuit 25 selects the output of the first pattern generator 24 and supplies it to the first AND circuit 27 . The first AND circuit 27 connects this and the second barrel shifter 3
The outputs of 1 are logically ANDed and the pattern (00000000
0000111) is output.

Now, one word of data (abcdefghijklmnop) set in the write data register 17 is shifted by 13 bits by the first barrel shifter 23, and becomes data (defghijklmnopabc). This data is supplied to the second AND circuit 32 and is ANDed with the pattern output from the first AND circuit 27. As a result, the data (000000000000abc
) is obtained. Further, the read data stored in the read data register 36 is ANDed with the pattern output from the second NOT circuit 33 by the third AND circuit 35. Here, the pattern output from the second knot circuit 33 is the pattern (00
This is a pattern (1111111111111000) that is the inversion of the logic of 0000000000111).

The logic output of the third AND circuit 35 is the logic output of the second AND circuit 32.
Output data 9 (000000000000abc
) are logically operated by the logic operation circuit 21. At this time, the logic operation circuit 21 is set by the mode register 19 to perform a logical sum. As a result, the logical operation circuit 21 outputs data in which the upper 13 bits are the upper 13 bits of the read data and the lower 3 bits are represented by "abc".

This data is supplied to the data terminal of the image memory 12 via the buffer 37 and written to the word address N.

When this writing to the image memory 12 is completed, the timing circuit 43 detects the carry signal 41 output from the adder 39. If this is not active, the operation ends.

When carry signal 41 is active, timing circuit 43 increments word address counter 13 by one and performs successive cycles on image memory 12. That is, data is read from address (N+1) and stored in the read data register 36. Further, the first selector circuit 25 is switched to select the output from the first NOT circuit 26. This allows the first
The output of the AND circuit 27 is (1000000000000
000), and the output of the second AND circuit 32 becomes (dooooooooooooooo). The read data is ANDed by the third AND circuit 35,
The upper 1 bit is "0" and the remaining 15 bits are the data represented by the lower 15 bits of the read data.

This data is logically summed by the logic operation circuit 21, and the upper 1 bit becomes "d" and the remaining 15 bits become data represented by the lower 15 bits of the read data. This data is written to address (N+1) of image memory 12. In this way, writing of the bit string "abcd" after bit address D of word address N is completed, and the series of operations ends.

Subsequently, a new address is set in the word address counter 13, and a write operation is performed by setting the previously set data in the write data register as data shifted by 4 bits. By performing the series of operations described above, the third address is set. Data will be written as shown in the figure.

〔Effect of the invention〕

As explained above, according to the present invention, a continuous bit string from the most significant bit to an arbitrary bit position in one word of write data can be written from an arbitrary bit address in the image memory by specifying replacement. Became. Therefore, the processing amount of the control processor can be reduced, and as a result, the processing speed when editing data to the image memory can be improved.

[Brief explanation of the drawing]

The drawings are for explaining one embodiment of the present invention, of which Fig. 1 is a block diagram showing an image memory and an image memory control circuit, and Fig. 2 (A) is an explanation showing data expressed in a matrix structure. FIG. 3B is an explanatory diagram when the data shown in FIG. 3A is expressed as serial data, and FIG. 3 is an explanatory diagram showing a part of the image memory. 11... Image memory control circuit, 12...
・Image memory, 13... Word address counter, 14...
... Bit address counter, 17 ... Write data register, 18 ... Bit length register, 19 ... Mode register, 21 ... Logical operation circuit, 23...First barrel pick, 24...First pattern generator, 26...
...First knot circuit, 29...Second pattern generator, 35...
...Third AND circuit, 39... Adder, 2
5...First selector circuit, 27...First AND circuit, 31...Second barrel switch, 32...Second AND circuit, 33... ...Second knot circuit, 36...Read data register. NEC Corporation NEC Data Equipment Co., Ltd.

Claims (1)

[Scope of Claims] A word address counter that stores a word address of an image memory; a bit address counter that stores a bit address of the image memory; a write data register that stores write data to the image memory; a bit length register that stores the bit length from the most significant bit of write data to an arbitrary bit position; a first barrel shifter that shifts the write data by a number equal to the value of the bit address; and a value of the bit address; a first pattern generator that generates a 1-word length pattern consisting of an equal number of consecutive signal "0"s and the remaining signal "1"; , the rest are a second pattern generator that generates a one-word length pattern represented by the signal "0", and a second barrel shifter that shifts the pattern output from the second pattern generator by a number equal to the value of the bit address. , a knot circuit that inverts the signal "1" and the signal "0" in the pattern output from the first pattern generator, and a first selector that selects one of the output of the first pattern generator and the output of the knot circuit. a first AND circuit that takes an AND of the first selector circuit and the output of the second barrel shifter; and a second AND circuit that takes an AND of the output of the first AND circuit and the output of the first barrel shifter. a third AND circuit that performs a logical product of a pattern obtained by inverting the signal “1” and the signal “0” at the output of the first AND circuit and the data read from the image memory; A logic operation circuit that performs a logic operation on the outputs of the second AND circuit and the third AND circuit, and adds the value of the bit address and the bit length value stored in the bit length register, and if the addition result is a numerical value of 16 or more. and an adder that outputs a signal that becomes active when An image memory control circuit characterized by writing.