JPS6341895A - Sequence control - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] By using a high-speed RAM as a memory for sequence control and writing sequence control data to this RAM from an external writing circuit, high-speed operation is possible and sequence control is possible. Disclosed is a sequence control method that allows changes to be made.

[Industrial application field]

The present invention relates to improvements in sequence control methods.

A sequence control circuit is a circuit that controls the operations of a controlled circuit in a predetermined order so that a given result is obtained in a given order.

For this purpose, control data is stored in a storage device in advance, and the data is sequentially read out in accordance with the progress of the count value of the counter and used for controlling the controlled circuit.

When a circuit that performs sequence control is incorporated into a part of a system, it is desirable that the sequence control process be executed at a desired speed without disturbing the operation of the entire system.

[Conventional technology]

An example of a conventional sequence control circuit will be described with reference to a block circuit diagram of a character generator shown in FIG.

The illustrated sequence control circuit reads horizontally written character data from the character generation ROM in the order of address numbers, writes it into a temporary storage device, and then reads the character data from the temporary storage device in the order of address numbers specified by the data stored in the sequence ROM. , output from the controlled circuit as vertical characters.

In the figure, the controlled circuit 1 includes a character generation ROM 11, a storage RAM 12, and an output section 13.

The sequence control circuit 10 includes a counter 3 , a sequence ROM 4 including a counter 5 , and a selector 2 .

The controlled circuit 1 once writes horizontally written characters read from the character generation RQM 11 into the RAM 12, and then converts them into vertically written characters using the sequence control circuit 10 and outputs them to the output section 13.

The selector 2 of the sequence control circuit 10 is a character generation ROM.
When writing 1l of data to RAM 12, counter 3
Connect to RAM12.

When selector 2 selects counter 3, character generation RO
The character pattern generated from M 11 is stored in RAM 12 according to the address determined by counter 3.

The relationship is shown in Figure 4 a) and b).

The character pattern a) consisting of 5 x 7 dots is stored in the RAM 12 by the counter 3 at sequential addresses O to 34.
Written in. At this time, black dots are stored as level 1 and white dots as level O.

Next, in order to make the character pattern a) vertically written, it is necessary to rotate the character pattern by 90 degrees.

For this purpose, selector 2 selects sequence ROM 4 from RA
Data is read out from the readout block ROl'l 4 in the order of its address number and supplied to the RAM 12 via the selector 2.

As is clear from Figure 4 a) and b), horizontally written characters are RA
If the addresses 4, 9, 14, .

Sequence ROM 4 is R in this address order.
It stores data for reading data from AM12.

The addresses and data on the sequence ROM are shown in FIG. 4C).

In the figure, data “00000100” at address O of the sequence ROM also has a value of “4” at address l.
The data "00001001" in "00001001" has a value of "9", and so on.

Data set in the ROM 4 can be arbitrarily selected. By selecting data to be stored in order of address numbers, it becomes possible to perform various sequence controls.

[Problem that the invention seeks to solve]

However, the control circuit using the above-mentioned sequence ROM has the disadvantage that the operating speed cannot be increased due to the circuit attached to the ROM itself.

Furthermore, it is difficult to change the sequence data stored in the ROM, and there is a problem in that even when there is a slight change in the sequence contents, separate new sequence data must be prepared.

For example, EFROM can be freely written and erased by the user, but its operating speed is slow. PROM operates faster than EPROM, but each time the sequence conditions change, a new RO
It has disadvantages such as requiring M.

[Means for solving problems]

The above problems are solved as shown in the principle diagram of the present invention in FIG.
Write circuit 2 for initial loading of sequence control data
This problem is solved by the sequence control circuit of the present invention, which is configured to write data from 0 to the sequence control RAM 7, read from the sequence control RAM 7 by the counter 9, and supply a control data signal to the controlled circuit 1.

[Effect]

According to the present invention, the initial loading of control data is performed by the write circuit 20. Sequence RA? The write address of +7 is specified by the write circuit 20, and the write address of selector 8
to the sequence RAl'l7. Further, data required for control is transmitted through the selector 6 to the sequence RA? 'l given to 7.

In the case of reading, the data written in the sequence RAM 7 in this manner is read out in accordance with the address designation of the read counter 9, and is applied to the controlled circuit 1 to execute desired sequence control.

The sequence control RAM is rewritable, and the written data can be changed every time the sequence control method is changed. Control data is written from a write circuit such as a low speed RO or processor.

Even though the control data is written at a low speed, the sequence control itself is executed at high speed because the sequence control RAM is used. Furthermore, although sequence control requires different control data depending on the circuit to be controlled, according to the present invention, it is easy to write and change the data, and there is no need to provide a new ROM each time. , the circuit becomes simple and easy.

〔Example〕

The present invention will be described in detail according to the illustrated embodiments.

FIG. 2 is a block diagram of the sequence control circuit of the present invention.

7 is RAM for storing sequence control data, 9 is RAM
'MHA output address generation counter (b) path, 8 a selector for address switching, 6 a selector for read/write switching, 21 a bus, 22 a processor for initializing data for sequence control; This corresponds to the circuit 20. Other parts that are the same as those in FIG. 3 and FIG. 1 are designated by the same numbers.

The controlled circuit 1 is sequence-controlled by data read from the sequence RAM 7 for sequence control.

Control data to RAM 7 is transferred to processor 2 during initial setting.
2, the selector 6.8 is switched and written.

At this time, control data for data writing is given from the processor 22 to the RAM 7 via the bus 21 and the selector 6.
The write address is given from the processor 22 via the lotus 21 and selector 8.

After writing, selector 6.8 is switched back. In this state, the counter 9 generates a read address for the sequence RAM 7, and the data read from the sequence RAM 7 according to this address is used for sequence control of the controlled circuit 1 via the selector 6 and the selector 2.

Although the processor 22 is used as the write circuit in this embodiment, it is also possible to use an EFROM for initial setting in other embodiments.

〔Effect of the invention〕

As described above, according to the present invention, a high-speed sequence control circuit is constructed, which can flexibly respond to changes in control conditions, and sequence conditions can be easily changed even in hardware debugging of complex control circuits. It is possible to do so, and its effects are extremely large.

[Brief explanation of drawings]

Fig. 1 is a principle diagram of the present invention, Fig. 2 is a block circuit diagram of a sequence control circuit in an embodiment of the present invention, Fig. 3 is a block circuit diagram of a conventional character generator, and Fig. 4 is an address of a storage device. and a data layout diagram. In the figure, 1 is the controlled circuit, 2.6.8 is the selector, 3.5.9 is the counter, 4 is the sequence ROM, 7 is the sequence RAM, 10
1 is a sequence control circuit, 11 is a character generation circuit, 12 is a RAM, 13 is an output section, and 22 is a processor. Figure 1 Figure 2 Block circuit diagram of conventional character generator Figure 3 Character generation ROM RAM
Nokens ROMa)
b) c) Storage device address and data allocation diagram Figure 4

Claims (1)

[Claims] Write circuit for initial loading of sequence control data (
20) to the sequence RAM (7), and the data written to the sequence RAM (7) is read by the counter (9) and supplied to the controlled circuit (1). Sequence control method.