JPS6223316B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a character size conversion device for enlarging or reducing a character pattern expressed by dots.

When enlarging or reducing a character pattern expressed by dots, for example, one character pattern consisting of 24 x 24 dots is decomposed into 3 x 3 sub-patterns, and these are divided into 4 x 4 sub-patterns with similar patterns. If you replace it with a partial pattern, the total is 4/3 times 32
The character pattern consists of ×32 dots.
This is simple as converting a character pattern to a non-integer multiple, but for example, if the line before conversion is as thick as two dots, then as will be explained in detail later, after conversion, the line within the same character will be In this case, the thickness may remain 2 dots, but in some places it may become 3 dots thick.

Another idea is a thinning/insertion method, in which a human determines and stores in advance information on where to thin out and where to insert in addition to character pattern information in a character pattern storage circuit. With this method, the thickness of the lines can be kept uniform, but the "bumps" that appear on the diagonal lines when enlarged are unavoidable. In your case, no ``bump'' occurs.

As described above, all conventional character pattern conversion methods have some problems.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a character size conversion device in which the line thickness after conversion does not vary within one character, and does not cause bumps in diagonal lines.

The character size conversion device of the present invention basically uses a partial pattern method to prevent the appearance of "bumps" in diagonal lines, and is also improved so that the line thickness does not vary within one character. It is.

That is, according to the present invention, there are provided a size indicating means for storing a size to be converted and issuing a size indicating signal, and a character pattern generating means for storing a character code of a basic size using dots and transmitting a character pattern of a series of continuous codes. , partial designating means for storing an address signal and emitting a signal to designate a part; and partial pattern extracting means for storing the transmitted character pattern and outputting a partial pattern of the designated part in response to the partial designation signal. , a control means in which selection information corresponding to each partial pattern is stored in advance for each size, and for emitting selection information corresponding to the outputted partial pattern as a selection signal at a size indicated by the size instruction signal; and each partial pattern. The output partial pattern is selected from among the plurality of types of partial patterns to be converted in the size indicated by the size instruction signal. A character size converting device is obtained, which includes partial pattern converting means for selecting and outputting any one partial pattern according to a signal.

Next, a detailed explanation will be given with reference to the drawings.

FIG. 1 is a diagram showing an example of a conversion table for conventional character size conversion for six typical patterns R1 to R6, shown for comparison in order to clarify the features of the present invention.

Figure 2 shows that when size conversion is performed using the conversion table in Figure 1, the thickness of the converted vertical line differs between cases (A) and (B) depending on how the partial pattern is taken. FIG. In this case, the problem is related to pattern R3 in Fig. 1. In (A), the two rows of dots before conversion are separated so that they are included in a single partial pattern, so The 3×3 partial pattern after conversion shows a vertical line consisting of three rows of dots, whereas in (B), the aforementioned two rows of dots are divided into two partial pattern rows. This indicates that the line will be a vertical line consisting of two rows of dots.
That is, when dividing a character pattern into partial patterns, the width of the vertical line (number of dot rows) differs depending on whether the boundary line passes through the vertical line on both sides or through the middle. Therefore, the conventional method has the disadvantage that the uniformity of the vertical lines cannot be maintained.

Figure 3 shows 2 before conversion in one embodiment of the present invention.
This is a diagram showing a character pattern composed of ×2 partial patterns, and the 24 × 24 dot pattern is 12 ×
It is decomposed into 12 partial patterns.

Figure 4 shows a conversion table that can convert each of the 2x2 partial patterns in Figure 3 into two types of 3x3 partial patterns, in this case 16 partial patterns that cover all dot arrangements. (Figure 1 also follows). Then, which of the two parallel 3×3 partial patterns after conversion is selected, the left or the right, is determined by the selection information provided in advance to each divided partial pattern.
It depends on whether the bit is "0" or "1".

FIG. 5 is a diagram showing the arrangement of the C bit shown in FIG. 4, that is, the selection information for the character pattern of FIG. 3 in a control memory (described later). The optimum arrangement has been selected by humans.

FIG. 6 is a diagram showing a character pattern obtained by enlarging the character pattern of FIG. 3 using the conversion table of FIG. 4 and the contents of the C bit of FIG. In Figure 6, the thickness of the vertical lines is 3 dots, and the width of the horizontal lines is 1 dot.As in Figure 2, which follows the conventional method, the thickness of the vertical lines is uniform. There is no such thing as lacking. Among the dots that make up the vertical lines in the figure, the dots marked with an x in the circle are if "0" (corresponding to the conventional conversion table in Figure 2) is set as the C bit in the conversion in S6 in Figure 4. It shows things that would not have appeared here if they had been used. Although other patterns are not shown in detail, a single 2×
Since two types of 3 x 3 partial patterns can be selected for almost all of the partial patterns in 2, the enlarged character pattern shown in Figure 6 is a better pattern than the conventional one even for things other than vertical and horizontal lines. There is.

In the present invention, four types of enlarged partial patterns may be provided as a conversion table, and two bits may be used as the C bit, or the number of types may be further increased. In this case, the type of table to be created is not necessarily fixed depending on the designer's intention (the same applies to Figures 1 and 4), but no matter what pattern is used, the size of the converted character pattern is The shape becomes better.

In the above examples, we have described enlargement to 3/2 times, but it is also possible to enlarge by 5/2, 4/3, 5/3, etc., and conversely, the same idea can be applied to reduction conversion. can do. Note that a reduction example will be explained later.

Next, the configuration and operation of a device that performs character size conversion will be explained.

FIG. 7 is a diagram showing the configuration of an embodiment of the present invention. In FIG. 7, first, an enlarged size signal a representing 3×3 dots is sent to an enlarged size register 21 from a device (not shown) that requires a character pattern.
is applied to and stored, and a size indication signal is issued (one of the branches is marked d). Next 2
A character code signal b of basic size represented by ×2 dots is stored in the character code register 22,
The output is converted into a series of continuous codes in the address conversion circuit 23. This conversion circuit is for converting, for example, a JIS Kanji code into a series of continuous codes. Furthermore, an address signal c indicating the position of a portion of the character pattern is stored in the portion register 24, and a signal indicating the portion is generated.

Character pattern memory 25 is address conversion circuit 2
It inputs a series of continuous codes from 3 and stores them, receives a partial instruction signal from the partial register 24, and outputs a signal e representing the specified partial pattern (2×2 dots). control memory 2
6 stores in advance the relationship between each partial pattern of the character pattern and the corresponding selection information for each address for each size (table C in FIG. When the code, the size instruction signal from the enlarged size register 21, and the partial instruction signal from the partial register 24 are received, the selection information, which in this case is "0" or "1" determined by these signals, is output as the selection signal f. Output. The partial pattern memory 27 that performs conversion of partial patterns has a conversion table in which two types of partial patterns are stored for each size, and each partial pattern is similar in size to the partial pattern. Upon receiving the signal e representing the converted partial pattern and the selection signal f, one of the two stored converted partial patterns is selected and output. Although the conversion partial pattern indicated by S1 in FIG. 4 is essentially one type, in this specification, it will be treated as formally stored as two types.

The output g of the partial pattern memory 27 is sent to the synthesis circuit 2.
8 to form a pattern of one character.
Note that instead of using the composition circuit 28, the output g of the partial pattern memory 27 may be directly printed on a printer (not shown) for each partial pattern to compose characters on paper.

In the character pattern conversion device described above, pattern conversion is performed using memory and addresses, but it is also possible to perform pattern conversion using logical operations. Therefore, in this embodiment, a case will be described in which a character pattern having a 4×4 partial pattern is converted to a character pattern having a 3×3 partial pattern.

FIG. 8 is a diagram showing a character pattern to be converted having 6×6 4×4 partial patterns to be converted (reduced) by logical operations.

Figure 9 shows the 4x4 dot name (A) that constitutes a partial pattern in the character pattern in Figure 8, and its 3
Dot name (B) when converted to ×3 partial pattern
FIG.

Although various forms of the operation of the Boolean algebraic expression in the conversion from (A) to (B) in FIG. 9 can be considered, the following two operations are preferably performed, for example.

() b ₁₁ = a ₁₁ , b ₁₂ = a ₁₂ + a ₁₃ , b ₁₃ = a ₁₄ , b ₂₁ =
a ₂₁ + a ₃₁ , b ₂₂ = a ₂₂ + a ₂₃ + a ₃₂ + a ₃₃ , b ₂₃ = a ₂₄ +
a ₃₄ , b ₃₁ = a ₄₁ , b ₃₂ = a ₄₂ + a ₄₃ , b ₃₃ = a ₄₄ () b ₁₁ = a ₁₁ , b ₁₂ = a ₁₂ , b ₁₃ = a ₁₃ + a ₁₄ , b ₂₁ =
a ₂₁ + a ₃₁ , b ₂₂ = a ₂₂ + a ₃₂ , b ₂₃ = a ₂₃ + a ₂₄ + a ₃₃ +
a ₃₄ , b ₃₁ = a ₄₁ , b ₃₂ = a ₄₂ , b ₃₃ = a ₄₃ + a ₄₄ The reason for performing the two operations as described above is for the C bits “0” and “1” in the previous example. This has the same meaning as providing two patterns. That is, based on the idea of the conventional conversion method, in this case, only the conversion using the operation () would be sufficient, but as will be explained in detail later, the uniformity of the vertical lines is lacking, so , the second calculation () is also performed, and one of the calculations can be selected depending on the pattern conversion situation.

Figure 10 shows a character pattern composed of reduced 3x3 partial patterns obtained as described above, where the vertical lines are two dot columns and the horizontal lines are single dot columns. are unified. In this case, only the two 3x3 subpatterns to which the dots marked with an x in the circle belong select the () operation, and many other subpatterns select the () operation. . The four dots marked with an x mark mean that if the operation () were selected for the partial pattern to which they belong based on conventional thinking, they would disappear. In other words, according to the conventional method, the vertical line becomes a single dot row in this part, which means that it lacks uniformity.

FIG. 11 is a block diagram showing the configuration of a circuit that performs the above two operations and selects one of them. It corresponds to the partial pattern memory 26 in FIG. 8, and the input and output signals are the same. It is indicated by a symbol. In FIG. 11, logic circuits 31 and 32 are circuits that receive the signal e from the character pattern memory 24 and the signal d from the size register 21 and perform the above-described operations () and (), respectively. When the signal f from the control circuit 25 is "0", the circuit 31 outputs, and when the signal f is "1", the circuit 32 outputs the output g. 33 is an inverting amplifier circuit.

As described above, according to the present invention, it is possible to maintain uniformity in line thickness after partial pattern conversion, and at the same time, it is possible to obtain more preferable shapes in other parts.

[Brief explanation of the drawing]

Figure 1 shows an example of a conversion table for conventional character size conversion, and Figure 2 shows case (A) when performing size conversion using the conversion table in Figure 1, depending on how the partial pattern is taken. Figure 3 is a diagram showing the difference in case (B), Figure 3 is a diagram showing a character pattern composed of 2x2 partial patterns before size conversion in an embodiment of the present invention, Figure 4 is a diagram showing an example of a conversion table for converting the 2×2 partial pattern in FIG. 3 to a 3×3 partial pattern, and FIG. 5 is the arrangement of the C bit shown in FIG. 4 in the control memory. FIG. 6 is a diagram showing a character pattern expanded from the character pattern in FIG. 3 using the conversion table in FIG. 4 and the contents of the C bit in FIG. 5.
Fig. 7 is a block diagram showing the configuration of an embodiment of the present invention, and Fig. 8 shows a character pattern to be converted having 6 x 6 4 x 4 partial patterns to be converted (reduced) by logical operations. The diagram shown, Figure 9, shows the dot names of the 4x4 partial pattern in Figure 8 (A) and the dot names of the partial pattern when this is reduced to a 3x3 partial pattern (B), respectively. Figure, 10th
The figure shows a character pattern consisting of a reduced 3x3 partial pattern obtained by performing the conversion in Figure 9 and two logical operations, and Figure 11 shows the character pattern formed by performing the two logical operations in Figure 10. FIG. 2 is a block diagram showing a circuit configuration of a portion that performs both operations and selects one of them. Explanation of symbols: 21 is the size register, 22 is the character code register, 23 is the address conversion circuit, 2
4 is a partial instruction register, 25 is a character pattern memory, 26 is a control memory, 27 is a partial pattern conversion circuit, 28 is a synthesis circuit, 31 and 32 are logic circuits, and 33 is an inverting amplifier circuit.

Claims (1)

[Claims] 1. Size instruction means that stores the size to be converted and issues a size instruction signal, character pattern generation means that stores the basic size character code of dots and sends out a character pattern of a series of continuous codes, and stores an address signal. Partial designating means for emitting a signal to designate a part; Partial pattern extracting means for storing the transmitted character pattern and outputting a partial pattern of the designated part in response to the partial designation signal; control means for storing selection information for each size in advance and for emitting selection information corresponding to the output partial pattern at the size indicated by the size instruction signal as a selection signal; The output partial pattern is selected from a plurality of types of partial patterns to be converted in the size indicated by the size instruction signal according to the selection signal. A character size conversion device comprising partial pattern conversion means for selecting and outputting two partial patterns.