JPS5937508B2 - Character pattern generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Printing by a soft printer or displaying characters by a cathode ray tube display device can be performed using signals obtained by reading character patterns stored in a character pattern memory. Known.

By the way, each character and the corresponding character pattern stored in the character pattern memory are stored in individual storage areas set to have a predetermined storage capacity, respectively. Therefore, the characters printed or displayed based on the information read from the character pattern memory are all aligned in a predetermined direction and orientation. Become.

On the other hand, when printing with a soft printer or displaying characters with a cathode ray tube display device, there are cases where there is a request to print or display characters horizontally or vertically (for example, for tabulations, drawings, etc.). Although such a request is often made in cases such as Conventionally, attempts to satisfy the above-mentioned demands have required the use of expensive electronic computers or software processing for converting bit arrays. However, there were problems such as the use of electronic computers was a heavy economic burden, and the software processing for converting the bit array required a long conversion time. The present invention has been made for the purpose of providing a character pattern generating device capable of solving the above-mentioned conventional problems. do. FIG. 1 is a block diagram of one embodiment of the character pattern generating device of the present invention. In this FIG. 1, TB is a memory (text buffer) for input character designation information, and M is a character pattern generator. memory,
CAC is a converter that converts input character designation information into a memory address signal indicating the start address of the storage area of the corresponding character pattern in the character pattern memory M to be designated by the input character designation information (this converter CAC is If the input character designation information in the FAR TB is a memory address signal indicating the start address of the storage area of the corresponding character pattern in the character pattern memory M to be designated by it, or the memory address signal ), the RD sends out multiple gate signals SGl to SG6, function control signals Fl, F2, etc. based on the rotation instruction code added to the input character designation information. Rotation instruction decoder, G1~G
6 is a gate circuit whose opening/closing is controlled by the gate signals SGl to SG6, 01 is a first arithmetic unit, and 02 is a second arithmetic unit.
arithmetic unit, ADD is an adder, MP is a multiplexer, C
Tx is a first N-ary counter that generates a signal indicating the horizontal position in the character pattern being printed or displayed when printing or display is performed by raster scanning; a second N-ary counter that generates a signal indicating the vertical position in the character pattern being printed or displayed when printing or displaying; SN is a generator of (N-1) numerical signals; be. The character pattern memory M described above stores data for each character and corresponding character pattern (N bits horizontally x N words vertically).
The storage area is set, and for example, it may be composed of a required number of ROM chips. In the following description of the embodiment, each character and the corresponding character pattern are individually stored in a storage area of N-32, that is, (32 bits horizontally x 32 bits vertically). However, in carrying out the present invention, it is arbitrary to decide what value N should be. Fig. 2a shows a model of the storage area in which a character pattern corresponding to a certain character in the character pattern memory M is stored, and the storage area shown in Fig. 2a is horizontally It is divided into 32 parts each in the vertical direction and 32×
It has a storage section of 32 units.

(A), 0), (1, 0)... shown in Figure 2 a.
Displays such as (31, 31) are coordinates indicating the position of each unit of storage portion in the storage area described above.

Figures 2b to 2e show that when the character pattern stored in the storage area shown in Figure 2a is A, printing can be done by changing the order in which information is read from the storage area. Alternatively, it is for illustrating and explaining how the characters to be displayed are rotated, and FIG. 2b shows how information is read from the storage area shown in FIG.
Coordinates (0,0)→(1,0)...→(31,0)1(
0,1)→(1,1)...→(31,1)→...→
Normal character pattern generation (0,31)→(1,31)...→(31,31)
Fig. 2c shows a case where information is read from the storage area shown in Fig. 2a at coordinates (31,0)→(31,1)... →(31,31)→
(30,0)→(30,1)...→(30,31)→
...→(0,0)→(0,1)...→(0,31)
Further, FIG. 2 d shows a case in which characters are generated at 900 rotations in the order shown in FIG.
,31)...→(0,31)→(31,30)→(3
0,30)...→(0,30)→...→(31,0
)→(30,0)...→(0,0), and FIG. Reading information from coordinates (0,31)→(0,30)...→(
0,0)→(1,31)→(1,30)...→(1,
0)→...→(31,31)→(31,30)...
This shows a case where characters are generated in 2700 rotations in the order such as →(31,0).

The number of times a rotated character pattern is read out from the character pattern memory M is determined by the character pattern rotation instruction code added to the input character designation information. For example, the instruction code is 0 for 00 rotations and 0 for 190 rotations.
It is set as 10 for 1.180 rotations and 11 for 2700 rotations. The character designation information to which the rotation command code of the character pattern is sent from the input character designation information memory TB is given to the rotation command decoder RD and the converter CAC, and the rotation command decoder R
At D, the rotation instruction code in the information given thereto is decoded to generate a plurality of gate signals SG1 to SG6 and function control signals Fl and F2.
G6 is individually given to each corresponding gate circuit G1 to G6,
Further, the function control signals Fl and F2 are applied to the corresponding arithmetic units 0 and 0, respectively.
,02 individually.

The open and closed states of each of the gate circuits G1 to G6 described above are expressed as 1,
0, and the first or second arithmetic circuit 01,0
The state of the function control signal F1 or F2 given individually to the arithmetic circuits 01 and 02 is 1 and 0, respectively.
When F1 (or F2) is 1, the operation performed on the two inputs A and b in 02 is as follows:
If C=a-b and O, and F, (or F2) is 0, then C=:a+b, 00, 900, 180-, 270 respectively from character pattern memory M.
5 of each gate circuit G1 to G6 to obtain an output that should produce a character pattern rotated by M.
Table 1 shows the open/close states and the states of the function control signals Fl and F2 to be given to each arithmetic circuit 01 and 02.

Among the gate circuits G1 to G6 described above, the gate circuit G
1 and G4 are a first N-ary counter CTx (implemented) which generates a signal Sx indicating the horizontal position in the character pattern being printed or displayed when printing or display is performed by raster scanning In the example, the signal Sx from the 32-digit counter) is controlled to open and close;
Further, the gate circuits G2 and G are connected to a second N-ary signal which generates a signal Sy indicating the vertical position in the character pattern being printed or displayed when printing or displaying is performed by raster scanning. The gate circuits G3 and G6 control the opening/closing of the signal Sy from the counter CTy (described as a 32-bin counter in the embodiment), and gate circuits G3 and G6 (
signal S from a generator SN (described in the example as a generator of 31 numerical signals) of 31 numerical signals;
Controls opening and closing of n.

Each of the above-mentioned signals Sx, Sy, and Sn is, for example, 2
Since it is expressed in evolved decimal numbers and is transmitted through five lines, each gate circuit G1 described above
~G6 is also composed of five gate circuits provided so as to correspond to the signals of each digit in each signal.

The output signals from the gate circuit G1 and the gate circuit G2 are
The signal b is input to the first arithmetic unit 01 via the OR circuit 0R1, and the output signals from the gate circuits G4 and G5 are input to the second arithmetic unit 02 as the signal b via the OR circuit 0R2. added as.

It goes without saying that the addition in the OR circuits 0R1 and 0R2 described above is performed between signals of the same digit in each signal, and this is true for the first and second arithmetic units 01 and 0, which will be described later.
In the case of calculations related to A and b signals in 2 and adder AD
The same applies to the addition operation in D, etc.

FIG. 3 is a block diagram showing a specific configuration example of the gate circuit portions indicated by Gl, G2, and G3 in FIG. 1, and the OR circuit portion indicated by 0R1. The configuration is the same for the gate circuit portions indicated by G4 to G6 in FIG. 1 and the OR circuit portion indicated by 0R2, so the corresponding components are shown in FIG. Each code is shown in brackets.

The content of the b signal of the two input signals A and b to the first and second arithmetic units 01 and 02, respectively, is based on each gate circuit G1 to G as shown in the first table above.
It changes depending on the open/closed state of 6, and each arithmetic unit 01,
Since the manner of calculation in 02 also changes depending on the states of the function control signals Fl and F2 as shown in Table 1 above, the output signals C from the first and second calculation units 01 and 02 are as follows. , it ends up changing depending on the rotation instruction code.

The output signal from the first arithmetic unit 01 is applied to the adder ADD, and the output signal from the second arithmetic unit 02 is applied as a control signal to the multiplexer MP. Since the above-mentioned adder ADD is supplied with a memory address signal indicating the start address of the storage area of the character pattern corresponding to the character to be specified by the input character specification information, the above-mentioned adder ADD The memory address signal given to the character pattern memory M moves the storage information in the storage area of the character pattern corresponding to the character to be specified by the input character designation information in a manner according to the rotation instruction code of the character pattern. The signal content is such that it can be read out, and the control signal given to the multiplexer MP from the second arithmetic unit 02 is a rotation instruction code of the character pattern from the information supplied to the multiplexer MP from the character pattern memory M. The multiplexer MP is controlled in such a way that an output signal is obtained having a signal content such that it can be printed or displayed as a character in a given state of rotation according to .

The storage area for each character pattern consisting of (N bits x N words) is (2n bits x 2n words).
, that is, in the case of N2n, the adder AD in FIG.
D is no longer necessary, and in this case, the output lines from the converter CAC and the first arithmetic unit 01 need only be directly input as lower address signals of the character pattern memory, making the configuration extremely simple. In addition, the configuration of the circuit for taking or not taking the complement in the first and second arithmetic units 01 and 02 is as shown in FIG. An advantage is obtained that it can be realized as an extremely simple structure that only performs the function of inverting or not inverting the polarity of each bit of each output signal from the forward counter CTy.

In FIG. 4, ANDl and AND2 are AND circuits, INl and INV2 are inverters, and 0R3 is an OR circuit. As is clear from the detailed explanation above, the character pattern generator of the present invention adds a character pattern rotation instruction code to the input character specification information in advance, and performs control according to the rotation instruction code. When printing or displaying is performed by raster scanning, a numerical signal indicating the horizontal position and a numerical signal indicating the vertical position in the character pattern being printed or displayed are converted into the complement of N. or add the value as it is to either or both of the address line of the character pattern memory or the control line of the multiplexer, or in any combination,
Moreover, it has a simple configuration in which an address signal indicating the start address of the storage area of the corresponding character pattern in the character pattern memory to be specified by the input character designation information is also added to the address line of the character pattern memory. , characters to be printed or displayed can be rotated by 00, 900, 180, and 270 while reading them from the character pattern memory. The problem is successfully resolved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the character pattern generation device of the present invention, FIGS.
3 and 4 are block diagrams of a part of the structure. TB...1 memo of input character designation information M...
...Character pattern memory, CAC...Converter, RD...Rotation instruction decoder, MP...
・Multiplexer, 01, 02... No.], No. 2
arithmetic unit, CTx...first N-ary counter, C
Ty...Second N-ary counter, G1 to G6...
...Gate circuit, 0R1-0R3...OR circuit, ADD...Adder.

Claims (1)

[Claims] 1. A character pattern memory in which a storage area of (N bits horizontally x N words vertically) is set for each character;
A multiplexer that sends out the information read from the character pattern memory as a character pattern output, and a multiplexer that sends out the information read from the character pattern memory as a character pattern output, and a plurality of gate signals and a a rotation instruction decoder that sends out function control signals, etc.; and a first device that generates a signal that indicates the horizontal position in a character pattern that is being printed or displayed when printing or display is performed by raster scanning. an N-ary counter, a second N-ary counter that generates a signal indicating the vertical position in the character pattern being printed or displayed when printing or display is performed by raster scanning; a generator of (N-1) numerical signals that performs calculations with the counted values of the first and/or second N-ary counter;
A gate circuit whose opening/closing is controlled by each gate signal output from the rotation instruction decoder described above, and the count values of the first and second N-ary counters and the numerical signal of (N-1), respectively. The corresponding character pattern in the character pattern memory to be specified by the first arithmetic unit input as an input via the gate circuit described above, and the output of the first arithmetic unit and the input character designation information. an adder that adds the address signal indicating the start address of the storage area and supplies the result as a memory address signal to the character pattern memory; and a second arithmetic unit which receives numerical signals as inputs through the aforementioned gate circuits and outputs a control signal to the aforementioned multiplexer.