JPS60236336A - Frame signal processor - Google Patents

Abstract

PURPOSE:To perform the frame signal processing with simple constitution by producing the address value after counting clocks to read out a ROM storing a prescribed bit pattern and controlling a gate. CONSTITUTION:Data are stored to a ROM403 so that the outputs of data lines (b)-(d) are changed in patterns corresponding to the prescribed time division number respectively from a read starting address through an address obtained by adding the number of bits equivalent to a frame. While such a data that turns the data (a) into ''1'' is stored to the address obtained by adding bits equivalent to a frame. When a frame signal is outputted from a CMI decoder 301, a counter 302 is reset to count clocks. This count value is supplied to the ROM403 as an address, and the contents of the address value are outputted to data lines (a)-(d) in synchronizing with clocks. Then gates 311-313 are switched. The decoding data fed from the decoder 301 are decomposed into frames for a control code, a PCM code and each video signal respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field 1] The present invention relates to a frame signal processing device, and more particularly to frame signal processing in which a time-divided frame signal is created from a plurality of signal sequences or decomposed into a plurality of signal sequences. It is related to the device.

[Prior art] Conventionally used frame communication methods, especially CM I
(Computer Managed In5truc
In the decoding process in the modulation method, a reproduced clock, a frame signal, and decoded data are formed during decoding, and the mainstream method is to use the frame signal as a reference and process subsequent data by time division.

Figure 1 shows an example of a signal having a frame structure commonly used in facsimile communication. Figure 1 (A) is a clock signal, and Figure 1 (CB) is one frame consisting of 192-bit serial data. It is a data signal.

Bit 0 of the data signal is a 1-bit control signal 2, and bits 1 to 8 are an 8-bit PCM code signal 3. There is a 183-bit data area after these data, but
Here, 87 bits from bits 9 to 95 are image signal 4.
The following 96 bits are used as an unused area. Further, the bit 192 between frames is 1 bit frame bit (y)1, and the frame is identified by this signal. At the time of decoding, based on the detection of this frame bit l, the
frame signals are formed.

The time-divided received data is decomposed into frames into each signal group and extracted, but at this time, as shown in Figure 2 (
The gate signals shown in A) to (D) are used. Figure 2 (
A) is a reset signal for taking out the frame signal l;
Figure 2 (B) shows the gate signal for extracting the control code signal, Figure 2 (C) shows the gate signal for extracting the PCM code signal, and Figure 2 (D) shows the gate signal for extracting the image signal. be.

Generation of gate signals during frame decomposition is performed by a circuit using a counter as shown in FIG. The reference numeral 301 in FIG. 3 is a known CMI decoder that decodes a CMI-modulated received signal to obtain a clock signal, a frame signal, and decoded data.

The decoded data generated by the CMI decoder 301 is input to AND gates 311, 312 and 313, and these gates are opened and closed by a counter circuit 302 and a gate signal generation circuit 304 to generate AND gates 311-31.
A control code, a PCM code signal, and an image signal are respectively decomposed into three outputs.

A decoded clock signal is input to an 8-bit counter 302, and an 8-bit count value is outputted from this counter 302. The bit pattern of this counter value is detected by count detection circuits 305 to 308 of the gate signal generation circuit 304, which is composed of decoder elements and the like. The count detection circuits 305 to 308 are r192J,
Kuzu detects the count values of "9", "l", and "0" (all decimal numbers).

The output of the count detection circuit 308 is configured to open an AND gate 311 via a signal line. This gate signal is the control code gate signal shown in FIG. 2(B).

Further, the outputs of count detection circuits 307 and 306 are outputted to 8-bit and 87-bit count circuits 310.3, respectively.
It is input in 09. The clock signal output from the CMI decoder 301 is input to the clock input of the count circuits 310 and 309. Count circuit 309.310
are triggered by count detectors 307 and 306, respectively, and output a high level to AND gates 313 and 312 via signal lines c and d while counting a predetermined number of pulses. The signals of these signal lines S and C are P in Fig. 2 (C) and (D).
These are gate signals for the CM code signal and image signal.

The output of the count detection circuit 305 is input to the OR game 303' via a signal line a. A frame signal output from the CMI decoder 301 is input to the other input of the OR gate 303, and the frame signal or the counter 3
By counting 192 clocks by 02, the counter 30
Reset 2. This reset signal is the reset signal shown in FIG. 2(A).

With the above circuit, the count detector 308 operates the AND gate 311 for bits 0 to 1, and the counter circuits 309 and 310 operate the AND gate 311 for bits 9 to 8 of each frame.
7 bits, and the game between bits l and 8 bits) 31
3.312 is opened, and the decomposed control code signal, PCM signal, and image signal are output to the output of each gate.

As described above, since the conventional frame decomposition generates a gate signal by counting clocks, it has the drawback that the circuit is complicated and a large number of parts are required. More time than the conventional example above! As the number increases, more circuits are required. Furthermore, the hardware configuration described above has the disadvantage that the circuit must be changed when the frame configuration changes, making it difficult to change the design.

Although the conventional example related to frame decomposition has been described above, a similar gate signal is formed by a circuit similar to that described above and is used when assembling a frame signal. Therefore, the above drawbacks are also common to frame assembly circuits.

[Objective] The present invention has been made in view of the above problems, and an object thereof is to provide a frame signal processing device that can perform frame signal processing with a simple and inexpensive structure.

[Example] Hereinafter, the present invention will be described in detail based on the example shown in the drawings. However, in the following description, the same or corresponding members as in the conventional example will be given the same reference numerals, and detailed explanation thereof will be omitted.

FIG. 4 shows an embodiment of the frame signal processing device according to the present invention. As shown in the figure, in the present invention, a ROM (read only memory) 403 is used for generating gate signals.
Use. Here, it is assumed that the ROM 403 is an 8-bit memory.

That is, the 8-bit count value of the counter 302 is R
It is given to OM403 as a read address. R.O.
Among the data lines of M403, predetermined data lines b-d (for example, three on the LSB side, etc.: here, d is LSB, c, b
and to be at the top. ) are each AND gate 3
It is connected to one input terminal of 11 to 313. The upper data line a of these three data lines is led to one input of the OR gate 303. and gate 31
The decoded data output from the CMI decoder 301 is input to the other inputs of CMI decoders 1 to 313, and the frame signal is input to the other input of the OR gate 303, as in the conventional example.

Data is stored in advance from the read start address of the ROM 403 to the address obtained by adding the number of bits for one frame so that the outputs of the data lines b to d change in a pattern according to the predetermined number of time divisions. , and data such that the data line a becomes "1" is stored at the address obtained by adding the number of bits of the l frame.

That is, when decomposing a signal having a frame structure similar to that shown in the conventional examples shown in FIGS. 1 and 2, if the read start address is set to address 0, rooo
oolooJ (binary number) and r in addresses 1 to 8.
ooooooloJ, and 87 bytes from address 9 store [OOo 000011, and (0
+192) roooooloooJ is stored at address.

The frame decomposition operation in the above configuration is performed as follows.

When a frame signal is output from the CMI decoder 301, the counter 302 is reset by this signal and starts counting clocks in order from 0. The 8-bit count value is input to the ROM 403 as an address value, and the contents of the address are output to data lines ad in synchronization with the clock. If the above pattern is written to each address, the AND gates 311 to 31 will be activated depending on the number of time division bits.
The gate signals No. 3 are switched in a pattern similar to the conventional one (see FIG. 2), and the control code signal, PCM code signal, and image signal can be subjected to frame decomposition.

According to the embodiments described above, there is an advantage that frame decomposition can be performed with a smaller number of circuits than in the conventional art. In particular, it is possible to control as many gates as the number of bits in a memory cell using basically the same circuit, and there is no need to change the hardware, and frame formats can also be changed without the need for hardware changes. Another advantage is that this can be done simply by changing the contents of the ROM 403.

In the above embodiment, the frame decomposition operation was explained, but
Of course, frame signals can be assembled using a similar configuration.

[Effect] As is clear from the above description, according to the present invention, in a frame signal processing device that creates or decomposes a time-divided frame signal from a plurality of signal sequences, the clock can be counted. storage means that stores a predetermined bit pattern at this address; and gate means that is controlled by the output data of this storage means. Since a disassembly configuration is adopted, it is possible to provide an excellent frame signal processing device that is simple, inexpensive, and allows for reliable frame disassembly and assembly processing with a configuration that does not require frequent design changes.

[Brief explanation of the drawing]

Figures 1 (A) to (C) to Figure 3 explain a conventional example, Figures 1 (A) to (C) are explanatory diagrams showing an example of the format of a frame signal, and Figure 2 (A) ) to (D) are sickle diagrams showing gate signals used for frame decomposition, Figure 3 is a block diagram showing the configuration of a conventional frame decomposition circuit, and Figure 4 is a block diagram showing the configuration of a conventional frame decomposition circuit.
The figure is a block diagram of a frame signal processing circuit according to the present invention. 301...CMI decoder 302...Counter 303...OR gates 311-313...AND gate 403...ROM

Claims (1)

[Claims] In a frame signal processing device that creates a time-divided frame signal from multiple signal streams or decomposes it into multiple signal streams, there is a means for counting clocks to generate an address value, and storing a predetermined bit pattern at this address. 1. A frame signal processing device comprising a storage means for storing data, and a gate means controlled by the output data of the storage means, the gate means assembling or disassembling a frame signal.