JP2000252835A - Coding circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a coding circuit by which an indefinite coded signal is not outputted through error concealment, even when the coding of an input signal is not finished within a predetermined period. SOLUTION: A frame A and a frame B to the frame A are inputted in succession to the coding circuit 100 as an input signal S100, a data processing means 102 encodes the frames A, B in order, a data storage means 103 stores processed data S1022 resulting from coding the frame A, an address and a size of the frame A are outputted as a head address S1020 and an output size S1021 until the coding of the frame B is finished, after the coding of the frame A has been finished. A counter 101 generates a frame signal S101 denoting a delimiter of the input signal, a data control means 104 latches the head address S1020 and the output size S1021 at the fall of the frame signal S101 and outputs them as an output address S1040, which is given to the data stream 103.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encoding circuit, and more particularly to an encoding circuit which performs concealment of an error when an error occurs during data encoding.

[0002]

2. Description of the Related Art Conventionally, a circuit having a configuration shown in FIG. 6 is known as a circuit for performing a signal processing for encoding and outputting a processed signal. For each block of the circuit shown in FIG.
The function will be described below.

[0003] Reference numeral 60 denotes a main body of a conventional encoding circuit.

[0004] In a frame unit process such as an MPEG audio encoder, an example of encoding using a frame signal S602 as a signal indicating the frame unit will be described.

An input terminal 601 receives a digitized input signal S601.

Reference numeral 602 denotes a counter, and the input signal S6
When "01" is input and the number of data is counted and reaches a certain count value, for example, a frame signal S602 indicating a frame delimiter is output.

[0007] Reference numeral 605 denotes a data storage means which stores the processing data S60 designated by the processing data address S604.
45 is exchanged with the data processing means 604. Further, the data specified by the output address S6035 is output as output data S605.

Reference numeral 603 denotes a data control unit which receives the frame signal S 602 and outputs an output address S 6035 for reading data to the data storage unit 605. The output address S6035 is the frame signal S602
Is controlled so that a predetermined output area 1 and an output area 2 of the data storage means 605 are alternately output at each falling edge of the data. Further, it outputs a valid signal S6037 indicating whether the output data S605 is valid or invalid.

A data processing unit 604 receives the input signal S 601 and the frame signal S 602, encodes the input signal S 601, and stores it in the data storage unit 605 via the processed data S 6045 and the processed data address S 604.

Reference numeral 606 denotes an output terminal, which is an input signal S601.
Is output to the outside.

An effective signal output terminal 607 outputs an effective signal S6037.

The circuit configured as described above encodes the input signal S601 and outputs the output signal S605.

[0013]

However, in recent years, in order to reduce the power consumption of equipment, the operating voltage has been reduced as necessary. In such a case, the processing speed is slowed down, so that the encoding time may be long. When such a technique is applied to the encoding circuit having the above configuration, there is a problem that if encoding is not completed in one frame time, indefinite data is output as encoded data.

An object of the present invention is to provide an encoding circuit which does not output an indefinite encoded signal by performing error concealment even when encoding of an input signal is not completed within a predetermined period. I do.

[0015]

According to a first aspect of the present invention, there is provided an encoding circuit for receiving data to be encoded and determining the number of time-series data of the data. Counting means for counting and outputting a frame signal which is a unit of encoding; storage means for storing encoded data; encoding the input data; storing encoded encoded data in the storage means; The first
Data processing means for outputting an address storing the encoded data of the first frame from completion of encoding of the first frame to completion of encoding of a second frame following the first frame. And a data control means for latching the address at every break of the frame signal and giving it as a read address of the storage means to output as encoded data.

According to the above configuration, when data of a certain frame is not completely encoded during a predetermined period, that is, one frame, instead of outputting indefinite data, encoding of a frame preceding the previous frame is performed. Since the data is output again, it is possible to prevent an indeterminate process from being performed at a later stage.

According to a second aspect of the present invention, there is provided an encoding circuit according to the first aspect, wherein the encoded data is such that the encoded data is valid or invalid. If the coding is not completed within one frame, the validity / invalidity information is set to indicate that the coded data is invalid. It is.

According to the above configuration, the processing in the case where the encoding is not completed in time can be performed in the subsequent stage of the encoding circuit, so that the degree of freedom of design is expanded. In addition, regarding the encoded data of the frame in which the valid / invalid information is invalid,
Since the data other than the valid / invalid information is the same as the data of the frame before the frame for which the encoding was not completed in time, the data does not become unstable so that the valid / invalid information cannot be analyzed. Can be analyzed.

According to a third aspect of the present invention, there is provided an encoding circuit according to the third aspect of the present invention, wherein the encoding circuit according to the first aspect of the present invention indicates whether the encoded data is valid or invalid. Further comprising an invalidation signal, wherein when the encoding of a certain frame is not completed within one frame, the validity / invalidity signal is determined so as to indicate that the encoded data is invalid. is there.

According to the above configuration, the circuit subsequent to the encoding circuit can obtain the same effect as that of the third embodiment only by decoding the binary signal of the valid / invalid signal without analyzing the valid / invalid information. .

According to a fourth aspect of the present invention, there is provided an encoding circuit according to the first aspect, wherein the storage means outputs the concealment data instead of the encoded data. After storing the data, the data processing means switches the address to the address where the concealment data is stored after a predetermined time after the encoding of the first frame is completed. When the encoding of the subsequent second frame is completed, the address is switched to the address storing the encoded data of the second frame.

According to the above configuration, when encoding of data of a certain frame is not completed within the time given to the encoding, concealment can be performed by replacing data of the frame with arbitrary data. it can.

According to a fifth aspect of the present invention, there is provided an encoding circuit according to the fifth aspect of the present invention, wherein the storage means stores a plurality of concealment data. The encoding circuit outputs an address of the concealment data in which concealment is inconspicuous.

According to the above configuration, when encoding of data of a certain frame is not completed within a time given to the encoding, concealment is performed by replacing data of the frame with more appropriate data. Can be.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS.

(Embodiment 1) FIG. 1 is a block diagram of an encoding circuit according to Embodiment 1 of the present invention. Less than,
Each block in FIG. 1 will be described.

Reference numeral 10 denotes a main body of the encoding circuit according to the first embodiment.

An input terminal 100 receives an input signal S100 for encoding.

Reference numeral 101 denotes a counter, which is an input signal S100.
Is counted, and when a predetermined number of data are input, a frame signal S101 is generated.

Reference numeral 102 denotes a data processing means, which is an input signal S
100, the frame signal S101 is input, the data is encoded, and the processing data address S1023 is output, thereby performing the encoding while exchanging the processing data S1022 in the middle of encoding with the data storage unit 103. In addition, an output size S1021 for indicating a start address S1020 and an end address of data read from the data storage unit 103 is output.

Numeral 103 denotes a data storage means, which is the processing data S10 designated by the processing data address S1023.
22 is exchanged with the data processing means 102. Also, it outputs the output data S103 read by the output address S1040.

Reference numeral 104 denotes a data control means, which is a frame signal S101, a head address S1020, an output size S1.
021, and outputs an address S1040 of data to be output to the data storage means 103 and a valid signal S1041 indicating whether the output data S103 is valid or not.

An output terminal 105 outputs an encoded signal.

Reference numeral 106 denotes a valid signal output terminal for outputting a valid signal S1041.

FIG. 2 shows the data storage means 103 shown in FIG.
FIG. 4 is a block diagram showing the details of. Hereinafter, each block in FIG. 2 will be described.

Frame signal S101, start address S1
020, output size S1021, output address S104
0 corresponds to the same sign shown in FIG.

Reference numeral 200 denotes an output data address start address storage unit which latches the start address S1020 at the falling edge of the frame signal S101 and outputs the address S200 held in synchronization with the frame signal S101.

Reference numeral 201 denotes output data size storage means.
The size S1021 is latched at the falling edge of the frame signal S101, and the size S201 held in synchronization with the frame signal S101 is output.

Reference numeral 202 denotes an address generation unit which receives the held address S200 and the held size S201 as inputs and outputs an output address S1040.

The operation of the coding circuit configured as described above will be described below.

(1) Error concealment by frame repeat FIG. 3 is a timing chart of the encoding circuit shown in FIG.

At time T0, encoding of frame B starts, and processed data S1022 which is data in the middle of encoding.
Is exchanged with the data storage means 103. Other signals are signals of the previous frame (frame A), and the description thereof is omitted.

At time T1, the encoding of frame B has already been completed, and the storage of data in data storage means 103 has also been completed. Then, the head address where the encoded frame B is stored, the head address S1020 which is the size thereof, and the output size S1021 are output.

At time T2, the frame signal S101 falls, the start address S1020, the output size S102
1 is latched and output as the held address S200 and the held size S201.

From time T2 to T3, the data control means 104 outputs the number of output addresses S1040 starting from the held address S200 specified by the held size S201. As a result, an address S1040 indicating the address where the frame B is stored is output, and the frame B is output from the data storage unit 103 as output data S103. At time T2, encoding of frame C starts. It should be noted that encoding of frame C does not end by time T4 when encoding of frame C must end.

At time T4, the frame signal S101 falls, but at this time, the encoding of the frame C has not been completed yet, the transfer of the data of the frame C to the processing data S1022 has not been completed, and the data processing has not been completed. The means 102 outputs the address and size of the frame B as the start address S1020 and the output size S1021. for that reason,
During the period in which the frame C is to be output, the held address S200 and the held size S201 still indicate the frame B, so the output address S104
0 indicates the address where the frame B is stored. The data in this area in the data storage means 103 is frame B
Has been encoded but is still stored, and the output data S10
3 is the same as frame B.

As can be seen from the above configuration and the description thereof, the processing data S1
022 is stored in the data storage unit 103 and the output size S1021 as the size of the start address S1020 is latched for each frame by the data control unit 104. Data storage means 1 stores the same frame as the frame.
03 can be read.

Also, by using the frame repeat function,
As a method of entrusting the error concealment to the decoding side, there is a method of setting an error value of a bit indicating whether an error has occurred or not in the error concealed frame, for example, a CRC bit. Then, error concealment can be left to the decoding side that receives the output without breaking the syntax of the output.

(Embodiment 2) FIG. 4 shows a memory configuration of the data storage means 104 for performing error concealment by outputting an arbitrary waveform when encoding cannot be performed in time. In the first frame, the work area 400
The data processing means 102 performs an encoding process using the output buffer 1 and the work area 401, and stores the processed data in the output buffer 1 and the work area 401. In the second frame, the data processing means 102 performs an encoding process using the work area 400 and the output buffer 2 / work area 402, and outputs the processed data to the output buffer 2 / work area 40.
2 is stored. The area indicated by the addresses A0 to A1 is an error concealment output buffer 403, in which arbitrary data to be output when an error occurs is stored. The configuration of the data storage unit 104 other than the error concealment output buffer 403 is the same as that shown in FIGS. 1 and 2 in the first embodiment.

FIG. 5 is a timing chart of the encoding circuit according to the second embodiment.

At time T0, encoding of frame B starts. Processing data S1022 which is data in the middle of the code
Is exchanged with the data storage means 103. At this time, the start address S1020 and the output size S1021 are switched so as to indicate the area from address A0 to A1 of the data storage means 103 (hereinafter referred to as concealment data Z). Other signals correspond to the previous frame, frame A, and the description thereof is omitted.

At time T0, encoding of frame B starts. At this time, since the start address S1020 and the output size S1021 each indicate a value corresponding to the previous frame, frame A, the held address S2
00 and the held size S201 are frame A
, And as a result, the encoded signal of frame A is output from the data storage means 103.

At time T1, the start address S102
0 and the output size S1021 are used to replace the indeterminate data in the middle of the code if the encoding of the frame B is not in time. It is temporarily changed to the indicated value. The time T1 may be any time before the encoding of the frame B is completed and until T3 when the frame signal S101 falls next. If the encoding of the frame B is completed, the time T1 may be any time. The value is returned to a value indicating the start address where B is stored and the size of frame B.

At time T2, the encoding of frame B is performed within the encoding time limit, that is, frame signal S10.
Since the processing ends before time T3, which is the time of the falling edge of No. 1, the start address S1020 and the output size S1021
To the one corresponding to frame B.

At time T3, the frame signal S101
Falls, the held address S200 and the held size S201 respectively indicate those corresponding to the frame B, and the encoded data of the frame B is output as the output data S103. Also, the next frame, frame C, is input, and encoding starts. Note that, in this case, the frame C has a time T at which the encoding must be completed.
Note that the encoding is not completed by 6.

At time T4, as in time T1, the start address S1020 and the output size S1021 are respectively the addresses of the concealment data Z in case that the encoding of the frame C has not been completed within the time limit. Is changed to a value indicating the size.

At time T5, the frame signal S101
Falls, but since the encoding of the frame C has not been completed, the start address S1020 and the output size S1021
Indicate the address and size of the concealment data Z, respectively, and the held address S200 and the held size size S201 indicate those corresponding to the concealment data Z, respectively. Therefore, concealment data Z is output to output data S103, and concealment data Z is output instead of outputting frame C as indefinite data during encoding.

At time T6, the encoding of frame C ends.
The start address S1020 and the output size S1021 indicate those corresponding to the frame C. In addition, encoding of the next frame, frame D, is started.

At time T7, the start address S1020 and the output size S102 are the same as at times T1 and T4.
1 is changed to a value indicating the concealment data Z.

At time T8, encoding of the frame D is completed, and the start address S1020 and the output size S1021 correspond to the frame D, respectively.

At time T9, the stored address S20
Since 0 and the held size S201 correspond to the frame D, the encoded data of the frame D is output as the output data S103. That is, concealment is released in this frame.

As described above, even if the encoding of a certain frame is not completed within a predetermined time, the data can be concealed into arbitrary data.

As a method of giving arbitrary concealment data Z, N (N is a natural number of 2 or more) data can be given. In this case, the level value at the beginning of the concealment is N different values from Ca0 to Can-1 and the level value at the end of the concealment is a fixed value common to Cb, and among these N patterns, 1
To choose one. As a method of selection, the value Ca0
If the data processing means 102 selects a value of .about.Can-1 which is closest to the value of the last data immediately before the start of the concealment, the most inconspicuous error concealment can be performed.

(Embodiment 3) As a method for skipping the data when an error occurs, the data processing means 102 outputs the output size S1021 as 0, and the data control means 104 Is output together with the output data S103 output by the data storage means 103, indicating that the data storage means 103 is valid or invalid. Thus, by deactivating the valid signal S1041 for a frame in which an error has occurred, it is possible to ignore the data on the decoding side.

[0065]

As described above, according to the present invention,
If the encoding of the data of a certain frame is not completed during a predetermined period, that is, the time of one frame, the encoded data of the frame preceding the frame is output again instead of outputting indefinite data. In addition, there is an effect that it is possible to prevent indeterminate processing from being performed in a subsequent stage.

[Brief description of the drawings]

FIG. 1 is a block diagram of an encoding circuit according to a first embodiment.

FIG. 2 is a block diagram of a data control unit 104 of the encoding circuit according to the first embodiment;

FIG. 3 is a timing chart showing an operation of the encoding circuit according to the first embodiment;

FIG. 4 is a block diagram of a data storage unit of the encoding circuit according to the second embodiment;

FIG. 5 is a timing chart showing an operation of the encoding circuit according to the second embodiment;

FIG. 6 is a block diagram of a conventional encoding circuit.

[Explanation of symbols]

 Reference Signs List 10 main body of encoding circuit of the present invention 100 input terminal 101 counter 102 data processing means 103 data storage means 104 data control means 105 data output terminal 106 valid signal output terminal

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Go Namba 1006 Kadoma Kadoma, Osaka Pref. Matsushita Electric Industrial Co., Ltd. Terms (reference) 5B001 AC01 AE02 5J064 AA00 BB12 BC01 BC02 BC05 BD01

Claims (5)

[Claims] 1. Counting means for inputting data to be encoded, counting the number of time-series data of the data and outputting a frame signal as a unit of encoding, and storing the encoded data. A storage unit, for encoding the input data, storing the encoded data in the storage unit, and a second frame following the first frame after the encoding of a certain first frame is completed.
Data processing means for outputting an address at which the encoded data of the first frame is stored until the encoding of the frame is completed; latching the address for each frame signal delimiter and reading the storage means A data control means for outputting as encoded data by giving as an address. 2. The coding circuit according to claim 1, wherein the coded data has valid / invalid information indicating whether the coded data is valid or invalid, and a certain frame is coded in one frame. If the encoding is not completed, the validity / invalidity information is determined so as to indicate that the encoded data is invalid. 3. The encoding circuit according to claim 1, further comprising a valid / invalid signal indicating whether the encoded data is valid or invalid, wherein the encoding of a certain frame is not completed within one frame. Wherein the valid / invalid signal is determined so as to indicate that the encoded data is invalid. 4. The encoding circuit according to claim 1, wherein the storage means stores concealment data to be output instead of the encoded data, and the data processing means encodes the first frame having an address. After a predetermined time from completion, the address is switched to the address storing the concealment data, and the second frame is encoded when the encoding of the second frame following the first frame is completed. An encoding circuit for switching to an address at which data is stored. 5. The encoding circuit according to claim 4, wherein said storage means stores a plurality of concealment data, and said data processing means outputs an address of said concealment data in which concealment is inconspicuous. Encoding circuit.