JPH02244886A - Buffer memory switching circuit - Google Patents

Abstract

PURPOSE:To read out plural buffer memories in use in a determined sequence by providing a buffer memory switching means switching a succeeding buffer memory according to the predetermined sequence when a prescribed pattern data read from a buffer memory is detected. CONSTITUTION:When an input frame data is subjected to coding processing by coding sections 41-4n, the processed data is sent to pattern generating means 61-6n whose processing end flag is corresponded when the coding processing is finished. The pattern generating means 61 writes the processing data when it is inputted and the prescribed pattern data when an end flag is written to the same area of a corresponding buffer memory 71. The processing data and the prescribed pattern data are read from the buffer memory 71, and when the prescribed pattern data is detected by a buffer memory switching section 8, the succeeding buffer memory is switched according to the predetermined sequence. Thus, when plural buffer memories are in use, the memories are read in the predetermined sequence.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a buffer memory switching circuit used in a device that digitally processes an analog video signal, and the purpose of this invention is to enable reading out in a predetermined order when multiple buffer memories are used. , normally the processed frame data output from the corresponding encoding unit is sent out as is, but when a processing end flag indicating that the encoding process is completed is input, predetermined pattern data is internally generated and sent out. a generating means, a buffer memory in which the processing frame data and predetermined pattern data sent from the pattern generating means are written to and read from the same address portion, and when detecting the predetermined pattern data read from the buffer memory; and buffer memory switching means for switching to the next buffer memory according to the determined order.

[Industrial application field]

The present invention relates to a buffer memory switching circuit used in a device that digitally processes an analog video signal.

Image processing apparatuses are often configured with one encoding section, and in this case, there is only one buffer memory into which data processed by the encoding section is written. Therefore, when reading processing data from this buffer memory, no problem arises in the reading order.

However, if multiple encoding processing units are provided and processing must be performed in parallel, there will be multiple corresponding buffer memories, so it is necessary to read data in a specified order regardless of the length of processing time. It is necessary.

[Conventional technology]

FIG. 5 shows a block diagram of a conventional example.

In the figure, an analog video signal from a camera 11 is applied to a preprocessing section 12.

The preprocessing section converts the analog signal into a digital signal, and uses digital signal processing to generate a luminance signal and two color signals C.
After being separated into 1 and C2, the eight color signals are time-compressed by taking advantage of their narrow bandwidth, and are further time-division multiplexed during the horizontal synchronization signal period of the luminance signal.

Then, the obtained time division multiplexed data (below).

After the input signal T[) (abbreviated as M data) is supplied to a prefilter to remove noise contained in the input signal, it is added to the encoding unit 13.

The encoding unit 13 performs predetermined predictive encoding on the input 70M data, further performs entropy encoding using variable length encoding and run length encoding, and writes the processed data into the buffer memory 14 . Since the buffer memory 14 uses clocks with different speeds between the encoding unit 13 and the transmission path, clock switching is performed.

Then, the processed data synchronized with the clock of the transmission line is subjected to error correction coding and scrambling processing in the line section 15, and then time-division multiplexed with eight human-generated voice encoders, etc., and sent out to the transmission line.

Also, the buffer memory 21. Decoding unit 22. Post-processing section 2
In part 3, the reverse processing to the above is performed to extract the analog video signal and display it on the monitor 24.

[Problem to be solved by the invention]

Now, since the encoding section is usually composed of one piece of hardware, the clock frequency supplied thereto is high, and one piece can encode 70M data. For this reason, there is only one buffer memory, but since it is configured with hardware, there is little flexibility in making changes.

Therefore, although encoding using a processor provides flexibility, there are cases in which encoding cannot be performed using a single processor.

In other words, a processor with approximately the same processing power as a hardened encoder has 3, for example, 100 machine cycles (the frequency of the clock supplied to the processor is 100 Mb).
ps) is required, but the actual processing capacity is 10~
20 machine cycles. Therefore, 5 to 10 processors must be used in parallel, and 5 to 10 buffer memories are also required accordingly.

Here, when one frame of data to be processed in a predetermined order is added to processors A, B, and C.

The encoding process for the data added to processor A is complicated.
Data added to processor B is easily encoded2
Assuming it is easy for processor C, processor B's processing ends first and the writing to the corresponding buffer memory ends, but processor A's processing is likely to end later.

At this time, if data is read from the buffer memory in the order in which the encoding process is completed, the original TDM signal will not be retrieved when decoding on the receiving side. There is a problem in that the corresponding buffer memory must be read.

The present invention is applicable when multiple buffer memories are used.

Predetermined order (order in which data is added to the buseser)
The purpose is to make it readable.

[Means to solve problems]

FIG. 1 shows a block diagram of the principle of the present invention.

In the figure, reference numeral 61 normally sends out the processed frame data output from the corresponding encoding unit as is.

A pattern generating means internally generates and sends predetermined pattern data when a process end flag indicating that the encoding process is completed is manually generated, and 71 is a pattern generator that generates and sends predetermined pattern data and the processed frame data sent from the button generating means. A buffer memory in which data is written to and read from the same address area.

Reference numeral 8 denotes buffer memory switching means for switching to the next buffer memory according to a predetermined order when the predetermined pattern data read out from the buffer memory is detected.

[Effect]

In the present invention, input time-division multiplexed data is added to n encoding units 41.4n for each predetermined frame in a predetermined order. When the encoding unit is encoding input frame data, it transmits the processed data, and when the encoding process is completed, it transmits a processing end flag to the corresponding pattern generation means 61, 6n.

Therefore, the pattern generation means 61 writes the predetermined pattern data in the same area of the corresponding buffer memo IJ71 when the processing data is inputted, and when the end flag is inputted.

Processing data and predetermined pattern data are read from the buffer memory 71, and when the buffer memory switching section 8 detects the predetermined pattern data, it switches to the next buffer memory in the above order and performs the same operation as above.

That is, the buffer memory switching section 8 does not switch the buffer memory while not detecting the predetermined pattern data, but switches to the next buffer memory after detecting it, so that the processed 70M data is sent to the outside.

〔Example〕

FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is an example of a block diagram of the unique word generator in FIG. 2, and FIG. 4 is an explanatory diagram of the operation of FIG. 2.

Note that the symbols on the left side of FIG. 4 indicate the waveforms of the portions with the same symbols in FIG. Also, a unique word generator 611. The selector 612 is a component of the pattern generation means 61, and the selector 81. A unique word detector 82 represents a component of the buffer memory switching section 8.

Hereinafter, n=3. The operation in Figure 2 will be explained with reference to Figures 3 and 4, assuming that TD) 1 signal is added to each encoder one frame at a time. conduct.

First, as shown in FIG.
1, each frame is distributed and added to the corresponding encoder. As a result, the encoding unit 41 outputs Nα1 as shown in FIG. 4-■. No, 4. Data of Nα7 frames are input sequentially.

The encoding unit 41 performs predictive encoding as described above in the order of input,
Further, entropy encoding using variable length encoding and run length encoding is performed for encoding processing, and the processed data is written to the buffer memory 71 via the selector 612 that selects the encoding unit side. When the processing is completed, the encoding unit 41 sends a processing end flag to the unique word generator (hereinafter abbreviated as UW generator) 611.

As shown in Figure 3, the UW generator is I? It is composed of an OM 611a, and a table for generating a UW pattern and a count operation table for counter operation are written in this ROM. Note that the first pattern is used to read out the data in the order in which it was written and to make it possible to distinguish between frames.

゛When the processing end flag is input, a switching signal is sent to the selector 612 and this selector is switched from the encoder side to the 120M side, so that the one pattern data generated in the ROM is transferred via the selector 612 to the buffer memory 71. sent to. Therefore, inside the buffer memory, a UW pattern is added to the Nri 1 malem as shown in FIG.

On the other hand, since the selector 81 shown in the second column selects the buffer memory 11 when the power is turned on, processing data and open pattern data are read out from the backup memory 71 and sent to the outside, but the U-detector 82 When detects U-pattern data, the selector switches to the buffer memory 72 based on the detection output of this detector, and the selector switches to the buffer memory 72.
Read the processing data from 2.

However, if the l]W pattern is not detected, the selector 81
does not switch to the buffer memory 72, but switches after an open pattern is detected.

This causes the encoder to have TD? The I data is read out from the backup memory in the order in which it was manually input.

That is, when using a plurality of buffer memories, they can be read in a predetermined order.

When using a plurality of memories, it has the advantage that they can be read in a predetermined order.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is an example of a block diagram of the unique word generator in Fig. 2, and Fig. 4 is a block diagram of the unique word generator in Fig. 2. FIG. 5 is a block diagram of the conventional example, and FIG. 6 is a diagram explaining the problem. In the figure, 8 is a puffer memory switching means, 41.4n is an encoding section, 6I is a pattern generating means, and 71 is a backup memory. [Effects of the Invention] As explained in detail above, according to the present invention, the 20th heavy duty of the buff 4. Heart 6. Tun B8 Figure 3

Claims (1)

[Claims] Input time-division multiplexed data is sequentially added to n encoding units (41, 4n) (41, 4n) for each predetermined frame in a predetermined order for processing. After that, when sending out the processed time-division multiplexed data, the processed frame data output from the corresponding encoding unit is normally sent as is, but if a processing end flag indicating that the encoding process has ended is input. A pattern generation means (61) that internally generates and sends predetermined pattern data.
a buffer memory (71) in which the processing frame data sent from the pattern generation means and predetermined pattern data are written to and read from the same address portion; and detecting the predetermined pattern data read from the buffer memory. buffer memory switching means (8) for switching to the next buffer memory according to the predetermined order;
) A buffer memory switching circuit characterized by having